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r01ds0031ej0210 rev.2.10 page 1 of 111 jul 31, 2012 m16c/65 group renesas mcu r01ds0031ej0210 rev.2.10 jul 31, 2012 datasheet 1. overview 1.1 features the m16c/65 group microcomputer (mcu) incorpor ates the m16c/60 series cpu core and flash memory, employing sophisticated instructions for a high level of efficiency. this mcu has 1 mb of address space (expandable to 4 mb), and it is capable of executing instructions at high speed. in addition, the cpu core boasts a multiplier for high-speed operation processing. this mcu consumes low power, and supports operati ng modes that allow additional power control. the mcu also uses an anti-noise configuration to reduce emissions of electromagnetic noise and is designed to withstand electromagnetic interference (emi). by in tegrating many of the perip heral functions, including the multifunction timer and serial interface, the number of sy stem components has been reduced. 1.1.1 applications this mcu can be used in audio components, cameras, televisions, household appliances, office equipment, communication devices, mobile device s, industrial equipment, and other applications.
r01ds0031ej0210 rev.2.10 page 2 of 111 jul 31, 2012 m16c/65 group 1. overview 1.2 specifications the m16c/65 group includes 128-pin and 100-pin pack ages. table 1.1 to table 1.4 list specifications. table 1.1 specifications for the 128-pin package (1/2) item function description cpu central processing unit m16c/60 series core (multiplier: 16 bit 16 bit 32 bit, multiply and accumulate instruction: 16 bit 16 bit + 32 bit 32 bit) ? number of basic instructions: 91 ? minimum instruction execution time: 31.25 ns (f(bclk) = 32 mhz, vcc1 = vcc2 = 2.7 to 5.5 v) ? operating modes: single-chip, memo ry expansion, and microprocessor memory rom, ram, data flash see table 1.5 ?produc t list (1/2)? and table 1.6 ?product list (2/2)?. voltage detection voltage detector ? power-on reset ? 3 voltage detection points (detection level of voltage detection 0 and 1 selectable) clock clock generator ? 5 circuits: main clock, sub clock, low-speed on-chip oscillator (125 khz), high-speed on-chip oscillator (40 mhz 10%), pll frequency synthesizer ? oscillation stop detection: main clock oscillation stop/restart detection function ? frequency divider circuit: divide ratio selectable from 1, 2, 4, 8, and 16 ? power saving features: wait mode, stop mode ? real-time clock external bus expansion bus memory expansion ? address space: 1 mb ? external bus interface: 0 to 8 waits inserted, 4 chip select outputs, memory area expansion function (expandable to 4 mb), 3 v and 5 v interfaces ? bus format: separate bus or multiplexed bus selectable, data bus width selectable (8 or 16 bits), number of address buses selectable (12, 16, or 20) i/o ports programmable i/o ports ? cmos i/o ports: 111 (selectable pull-up resistors) ? n-channel open drain ports: 3 interrupts ? interrupt vectors: 70 ? external interrupt inputs: 13 ( nmi , int 8, key input 4) ? interrupt priority levels: 7 watchdog timer 15-bit timer 1 (with prescaler) automatic reset start function selectable dma dmac ? 4 channels, cycle steal mode ? trigger sources: 43 ? transfer modes: 2 (single transfer, repeat transfer)
r01ds0031ej0210 rev.2.10 page 3 of 111 jul 31, 2012 m16c/65 group 1. overview notes: 1. see table 1.5 ?product list (1/2)? and table 1.6 ?product list (2/2)? for the operating temperature. 2. the cec function indicates circuitry which supports the transmission and reception of cec signals standardized by the high-definition multimedia interface (hdmi) . hdmi and high-definition multimedia interface are registered trademarks of hdmi licensing, llc. table 1.2 specifications for the 128-pin package (2/2) item function description timers timer a 16-bit timer 5 timer mode, event counter mode, one-shot timer mode, pulse width modulation (pwm) mode event counter two-phase pulse si gnal processing (two-phase encoder input) 3 programmable output mode 3 timer b 16-bit timer 6 timer mode, event counter mode, pulse period measurement mode, pulse width measurement mode three-phase motor control timer functions ? three-phase inverter control (timer a1, timer a2, ti mer a4, timer b2) ? on-chip dead time timer real-time clock count: seconds, minutes, hours, days of the week pwm function 8 bits 2 remote control signal receiver ? 2 circuits ? 4 wave pattern matchings (differentiate wave pattern for headers, data 0, data 1, and special data) ? 6-byte receive buffer (1 circuit only) ? operating frequency of 32 khz serial interface uart0 to uart2, uart5 to uart7 clock synchronous/asynchronous 6 channels i 2 c-bus, iebus, special mode 2 sim (uart2) si/o3, si/o4 clock synchronization only 2 channels multi-master i 2 c-bus interface 1 channel cec functions (2) cec transmit/receive, arbitration lost detection, ack automatic output, operation frequency of 32 khz a/d converter 10-bit resolution 26 channels, including sample and hold function conversion time: 1.72 s d/a converter 8-bit resolution 2 circuits crc calculator crc-ccitt (x 16 + x 12 + x 5 + 1), crc-16 (x 16 + x 15 + x 2 + 1) compliant flash memory ? program and erase power suppl y voltage: 2.7 to 5.5 v ? program and erase cycles: 1,000 ti mes (program rom 1, program rom 2), 10,000 times (data flash) ? program security: rom code protect, id code check debug functions on-chip debug, on-board fl ash rewrite, address match interrupt 4 operation frequency/supply voltage 32 mhz/vcc1 = 2.7 to 5.5 v, vcc2 = 2.7 v to vcc1 current consumption described in electrical characteristics operating temperature -20c to 85c, -40c to 85c (1) package 128-pin lqfp: plqp0128kb-a (previous package code: 128p6q-a)
r01ds0031ej0210 rev.2.10 page 4 of 111 jul 31, 2012 m16c/65 group 1. overview table 1.3 specifications for the 100-pin package (1/2) item function description cpu central processing unit m16c/60 series core (multiplier: 16 bit 16 bit 32 bit, multiply and accumulate instruction: 16 bit 16 bit + 32 bit 32 bit) ? number of basic instructions: 91 ? minimum instruction execution time: 31.25 ns (f(bclk) = 32 mhz, vcc1 = vcc2 = 2.7 to 5.5 v) ? operating modes: single-chip, memo ry expansion, and microprocessor memory rom, ram, data flash see table 1.5 ?produc t list (1/2)? and table 1.6 ?product list (2/2)?. voltage detection voltage detector ? power-on reset ? 3 voltage detection points (detection level of voltage detection 0 and 1 selectable) clock clock generator ? 5 circuits: main clock, sub clock, low-speed on-chip oscillator (125 khz), high-speed on-chip oscillator (40 mhz 10%), pll frequency synthesizer ? oscillation stop detection: main clock oscillation stop/restart detection function ? frequency divider circuit: divide ratio selectable from 1, 2, 4, 8, and 16 ? power saving features: wait mode, stop mode ? real-time clock external bus expansion bus memory expansion ? address space: 1 mb ? external bus interface: 0 to 8 waits inserted, 4 chip select outputs, memory area expansion function (expandable to 4 mb), 3 v and 5 v interfaces ? bus format: separate bus or multiplexed bus selectable, data bus width selectable (8 or 16 bits), number of address buses selectable (12, 16, or 20) i/o ports programmable i/o ports ? cmos i/o ports: 85 (selectable pull-up resistors) ? n-channel open drain ports: 3 interrupts ? interrupt vectors: 70 ? external interrupt inputs: 13 ( nmi , int 8, key input 4) ? interrupt priority levels: 7 watchdog timer 15-bit timer 1 (with prescaler) automatic reset start function selectable dma dmac ? 4 channels, cycle steal mode ? trigger sources: 43 ? transfer modes: 2 (single transfer, repeat transfer)
r01ds0031ej0210 rev.2.10 page 5 of 111 jul 31, 2012 m16c/65 group 1. overview notes: 1. see table 1.5 ?product list (1/2)? and table 1.6 ?product list (2/2)? for the operating temperature. 2. the cec function indicates circuitry which supports the transmission and reception of cec signals standardized by the high-definition multimedia interface (hdmi) . hdmi and high-definition multimedia interface are registered trademarks of hdmi licensing, llc. table 1.4 specifications for the 100-pin package (2/2) item function description timers timer a 16-bit timer 5 timer mode, event counter mode, one-shot timer mode, pulse width modulation (pwm) mode event counter two-phase pulse si gnal processing (two-phase encoder input) 3 programmable output mode 3 timer b 16-bit timer 6 timer mode, event counter mode, pulse period measurement mode, pulse width measurement mode three-phase motor control timer functions ? three-phase inverter control (timer a1, timer a2, ti mer a4, timer b2) ? on-chip dead time timer real-time clock count: seconds, minutes, hours, days of the week pwm function 8 bits 2 remote control signal receiver ? 2 circuits ? 4 wave pattern matchings (differentiate wave pattern for headers, data 0, data 1, and special data) ? 6-byte receive buffer (1 circuit only) ? operating frequency of 32 khz serial interface uart0 to uart2, uart5 to uart7 clock synchronous/asynchronous 6 channels i 2 c-bus, iebus, special mode 2 sim (uart2) si/o3, si/o4 clock synchronization only 2 channels multi-master i 2 c-bus interface 1 channel cec functions (2) cec transmit/receive, arbitration lost detection, ack automatic output, operation frequency of 32 khz a/d converter 10-bit resolution 26 channels, including sample and hold function conversion time: 1.72 s d/a converter 8-bit resolution 2 circuits crc calculator crc-ccitt (x 16 + x 12 + x 5 + 1), crc-16 (x 16 + x 15 + x 2 + 1) compliant flash memory ? program and erase power suppl y voltage: 2.7 to 5.5 v ? program and erase cycles: 1,000 ti mes (program rom 1, program rom 2), 10,000 times (data flash) ? program security: rom code protect, id code check debug functions on-chip debug, on-board fl ash rewrite, address match interrupt 4 operation frequency/supply voltage 25 mhz/vcc1 = 2.7 to 5.5 v, vcc2 = 2.7 v to vcc1 32 mhz/vcc1 = 2.7 to 5.5 v, vcc2 = 2.7 v to vcc1 current consumption described in electrical characteristics operating temperature -20c to 85c, -40c to 85c (1) package 100-pin qfp: prqp0100jd-b (previous package code: 100p6f-a) 100-pin lqfp: plqp0100kb-a (previous package code: 100p6q-a)
r01ds0031ej0210 rev.2.10 page 6 of 111 jul 31, 2012 m16c/65 group 1. overview 1.3 product list table 1.5 and table 1.6 list product information. figure 1.1 shows the part no., with memory size and package, and figure 1.2 shows the marking diagram (top view). (d): under development (p): planning previous package codes are as follows: plqp0128kb-a: 128p6q-a prqp0100jd-b: 100p6f-a plqp0100kb-a: 100p6q-a table 1.5 product list (1/2) as of july 2012 part no. rom capacity ram capacity package code remarks program rom 1 program rom 2 data flash r5f36506nfa 128 kb 16 kb 4 kb 2 blocks 12 kb prqp0100jd-b operating temperature -20c to 85c r5f36506nfb plqp0100kb-a r5f36506dfa prqp0100jd-b operating temperature -40c to 85c r5f36506dfb plqp0100kb-a r5f3651enfc 256 kb 16 kb 4 kb 2 blocks 20 kb plqp0128kb-a operating temperature -20c to 85c r5f3650enfa prqp0100jd-b r5f3650enfb plqp0100kb-a r5f3651edfc plqp0128kb-a operating temperature -40c to 85c r5f3650edfa prqp0100jd-b r5f3650edfb plqp0100kb-a r5f3651knfc 384 kb 16 kb 4 kb 2 blocks 31 kb plqp0128kb-a operating temperature -20c to 85c r5f3650knfa prqp0100jd-b r5f3650knfb plqp0100kb-a r5f3651kdfc plqp0128kb-a operating temperature -40c to 85c r5f3650kdfa prqp0100jd-b r5f3650kdfb plqp0100kb-a r5f3651mnfc 512 kb 16 kb 4 kb 2 blocks 31 kb plqp0128kb-a operating temperature -20c to 85c r5f3650mnfa prqp0100jd-b r5f3650mnfb plqp0100kb-a r5f3651mdfc plqp0128kb-a operating temperature -40c to 85c r5f3650mdfa prqp0100jd-b r5f3650mdfb plqp0100kb-a r5f3651nnfc 512 kb 16 kb 4 kb 2 blocks 47 kb plqp0128kb-a operating temperature -20c to 85c r5f3650nnfa prqp0100jd-b r5f3650nnfb plqp0100kb-a r5f3651ndfc plqp0128kb-a operating temperature -40c to 85c r5f3650ndfa prqp0100jd-b r5f3650ndfb plqp0100kb-a r5f3651rnfc 640 kb 16 kb 4 kb 2 blocks 47 kb plqp0128kb-a operating temperature -20c to 85c r5f3650rnfa prqp0100jd-b r5f3650rnfb plqp0100kb-a r5f3651rdfc plqp0128kb-a operating temperature -40c to 85c r5f3650rdfa prqp0100jd-b r5f3650rdfb plqp0100kb-a
r01ds0031ej0210 rev.2.10 page 7 of 111 jul 31, 2012 m16c/65 group 1. overview (d): under development (p): planning previous package codes are as follows: plqp0128kb-a: 128p6q-a prqp0100jd-b: 100p6f-a plqp0100kb-a: 100p6q-a table 1.6 product list (2/2) as of july 2012 part no. rom capacity ram capacity package code remarks program rom 1 program rom 2 data flash r5f3651tnfc 768 kb 16 kb 4 kb 2 blocks 47 kb plqp0128kb-a operating temperature -20c to 85c r5f3650tnfa prqp0100jd-b r5f3650tnfb plqp0100kb-a r5f3651tdfc plqp0128kb-a operating temperature -40c to 85c r5f3650tdfa prqp0100jd-b r5f3650tdfb plqp0100kb-a
r01ds0031ej0210 rev.2.10 page 8 of 111 jul 31, 2012 m16c/65 group 1. overview figure 1.1 part no., with memory size and package figure 1.2 marking diagram (top view) package type fc: package plqp0128kb-a (128p6q-a) fa: package prqp0100jd-b (100p6f-a) fb: package plqp0100kb-a (100p6q-a) property code n: operating temperature: -20c to 85c d: operating temperature: -40c to 85c memory type f: flash memory r 5 f 3 6 5 0 6 d fa renesas mcu renesas semiconductor m16c/65 group memory capacity program rom 1/ram 6: 128 kb/12 kb e: 256 kb/20 kb k: 384 kb/31 kb m: 512 kb/31 kb n: 512 kb/47 kb r: 640 kb/47 kb t: 768 kb/47 kb 16-bit mcu part no. number of pins 0: 100 pins 1: 128 pins m16c r5f36506dfa xxxxxxx type no. running no. 0 to 9, a to z (except for i, o, q) week code (from 01 to 54) last digit of year (see figure 1.1 ?part no., with memory size and package?)
r01ds0031ej0210 rev.2.10 page 9 of 111 jul 31, 2012 m16c/65 group 1. overview 1.4 block diagram figure 1.3 to figure 1.4 show block diagrams. figure 1.3 block diagram for the 128-pin package dmac (4 channels) internal peripheral functions uart or clock synchronous serial i/o (6 channels) system clock generator xin-xout xcin-xcout pll frequency synthesizer on-chip oscillator (125 khz) high-speed on-c hip oscillator clock synchronous serial i/o (8 bit x 2 channels) notes: 1. rom size depends on mcu type. 2. ram size depends on mcu type. 8 8 8 8 8 8 port p5 port p4 port p3 port p2 port p1 port p0 vcc2 ports m16c/60 series cpu core r1h r1l r0h r0l r3 r2 a0 a1 fb multiplier rom (1) memory ram (2) sb isp usp intb pc flg crc arithmetic circuit (crc-ccitt or crc-16) three-phase motor control circuit timer (16 bit) outputs (timer a): 5 inputs (timer b): 6 vcc1 ports real-time clock pwm function (8 bit x 2) remote control signal receiver (2 circuits) watchdog timer (15 bit) a/d converter (10-bit resolution x 26 channels) d/a converter (8-bit resolution x 2 circuits) multi-master i 2 c-bus interface (1 channel) cec function 8 8 port p13 port p12 port p7 port p8 port p9 port p6 2 port p14 port p11 port p10 8 8 8 8 8 8 on-chip debugger voltage detector power-on reset
r01ds0031ej0210 rev.2.10 page 10 of 111 jul 31, 2012 m16c/65 group 1. overview figure 1.4 block diagram for the 100-pin package dmac (4 channels) internal peripheral functions uart or clock synchronous serial i/o (6 channels) system clock generator xin-xout xcin-xcout pll frequency synthesizer on-chip oscillator (125 khz) high-speed on-c hip oscillator clock synchronous serial i/o (8 bit x 2 channels) notes: 1. rom size depends on mcu type. 2. ram size depends on mcu type. 8 8 8 8 8 8 port p5 port p4 port p3 port p2 port p1 port p0 vcc2 ports m16c/60 series cpu core r1h r1l r0h r0l r3 r2 a0 a1 fb multiplier rom (1) memory ram (2) sb isp usp intb pc flg crc arithmetic circuit (crc-ccitt or crc-16) three-phase motor control circuit 8 8 8 port p7 port p8 port p9 port p10 8 port p6 8 timer (16 bit) outputs (timer a): 5 inputs (timer b): 6 vcc1 ports real-time clock pwm function (8 bit x 2) remote control signal receiver (2 circuits) watchdog timer (15 bit) a/d converter (10-bit resolution x 26 channels) d/a converter (8-bit resolution x 2 circuits) multi-master i 2 c-bus interface (1 channel) cec function on-chip debugger voltage detector power-on reset
r01ds0031ej0210 rev.2.10 page 11 of 111 jul 31, 2012 m16c/65 group 1. overview 1.5 pin assignments figure 1.5 to figure 1.7 show pin assignments. table 1.7 to table 1.11 list pin names. figure 1.5 pin assignment for the 128-pin package 1 m16c/65 group plqp0128kb-a (128p6q-a) (top view) 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 78 77 76 75 74 73 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 31 32 33 34 35 36 37 71 70 69 68 67 66 72 38 65 64 vcc1 xin xout vss reset cnvss p8_7/xcin p8_6/xcout byte p7_4/ta2out/w p5_6/ale p5_5/hold p5_4/hlda p5_3/bclk p5_2/rd p5_7/rdy/clkout p6_3/txd0/sda0 p6_5/clk1 p6_6/rxd1/scl1 p6_7/txd1/sda1 p6_1/clk0 p6_2/rxd0/scl0 p9_5/anex0/clk4 p9_6/anex1/sout4 p6_4/cts1/rts1/cts0/clks1 p8_2/int0 p8_3/int1 p5_0/wrl/wr p5_1/wrh/bhe p9_0/tb0in/clk3 p7_2/clk2/ta1out/v p8_4/int2/zp p7_3/cts2/rts2/ta1in/v p7_5/ta2in/w vref avcc p9_7/adtrg/sin4 p14_1 p14_0 p13_7 p13_6 p13_5 p13_4 p3_1/a9 p3_2/a10 p3_3/a11 p3_4/a12 p3_5/a13 p3_6/a14 p3_7/a15 p4_0/a16 p4_1/a17 p4_2/a18 p4_3/a19 vcc2 vss p12_4 p12_3 vcc1 vss p13_0 p13_1 p13_2 p13_3 p12_5 p12_6 p12_7 p12_2 p12_1 p12_0 vcc2 ports vcc1 ports notes: 1. n-channel open drain output. 2. check the position of pin 1 by refe rring to appendix 1, package dimensions. 3. pin names in brackets [ ] r epresent a single functional signal. they should not be considered as two separate functional signals. p7_6/ta3out/txd5/sda5 p7_7/ta3in/clk5 p8_0/ta4out/u/rxd5/scl5 p8_1/ta4in/u/cts5/rts5 p4_5/clk7/cs1 p4_4/cts7/rts7/cs0 p3_0/a8 [a8/d7] p2_0/an2_0/a0, [a0/d0], a0 p2_1/an2_1/a1, [a1/d1], [a1/d0] p2_2/an2_2/a2, [a2/d2], [a2/d1] p2_3/an2_3/a3, [a3/d3], [a3/d2] p2_4/int6/an2_4/a4, [a4/d4], [a4/d3] p2_5/int7/an2_5/a5, [a5/d5], [a5/d4] p2_7/an2_7/a7, [a7/d7], [a7/d6] see note 3 p2_6/an2_6/a6, [a6/d6], [a6/d5] p1_4/d12 p1_1/clk6/d9 p1_2/rxd6/scl6/d10 p1_3/txd6/sda6/d11 p1_5/int3/idv/d13 p1_6/int4/idw/d14 p1_7/int5/idu/d15 p4_6/pwm0/rxd7/scl7/cs2 p4_7/pwm1/txd7/sda7/cs3 p6_0/rtcout/cts0/rts0 p7_0/txd2/sda2/sdamm/ta0out (1) p7_1/rxd2/scl2/sclmm/ta0in/tb5in (1) p8_5/nmi/sd/cec (1) p9_1/tb1in/pmc1/sin3 p9_2/tb2in/pmc0/sout3 p9_3/da0/tb3in/pwm0 p9_4/da1/tb4in/pwm1 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 p0_0/an0_0/d0 p0_1/an0_1/d1 p0_2/an0_2/d2 p0_3/an0_3/d3 p0_4/an0_4/d4 p0_5/an0_5/d5 p0_6/an0_6/d6 p0_7/an0_7/d7 avss p10_0/an0 p10_1/an1 p10_2/an2 p10_3/an3 p10_7/an7/ki3 p10_6/an6/ki2 p10_5/an5/ki1 p10_4/an4/ki0 p11_3 p11_2 p11_1 p11_0 p11_4 p11_5 p11_6 p11_7 p1_0/cts6/rts6/d8
r01ds0031ej0210 rev.2.10 page 12 of 111 jul 31, 2012 m16c/65 group 1. overview table 1.7 pin names for the 128-pin package (1/3) pin no. control pin port i/o pin for peripheral function bus control pin interrupt timer serial interface a/d converter, d/a converter 1vref 2avcc 3 p9_7 sin4 adtrg 4 p9_6 sout4 anex1 5 p9_5 clk4 anex0 6 p9_4 tb4in/pwm1 da1 7 p9_3 tb3in/pwm0 da0 8 p9_2 tb2in/pmc0 sout3 9 p9_1 tb1in/pmc1 sin3 10 p9_0 tb0in clk3 11 p14_1 12 p14_0 13 byte 14 cnvss 15 xcin p8_7 16 xcout p8_6 17 reset 18 xout 19 vss 20 xin 21 vcc1 22 p8_5 nmi sd cec 23 p8_4 int2 zp 24 p8_3 int1 25 p8_2 int0 26 p8_1 ta4in/ uc t s 5 / rts5 27 p8_0 ta4out/u rxd5/scl5 28 p7_7 ta3in clk5 29 p7_6 ta3out txd5/sda5 30 p7_5 ta2in/ w 31 p7_4 ta2out/w 32 p7_3 ta1in/ vc t s 2 / rts2 33 p7_2 ta1out/v clk2 34 p7_1 ta0in/tb5in rxd2/scl2/sclmm 35 p7_0 ta0out txd2/sda2/sdamm 36 p6_7 txd1/sda1 37 vcc1 38 p6_6 rxd1/scl1 39 vss 40 p6_5 clk1 41 p6_4 cts1 / rts1 / cts0 /clks1 42 p6_3 txd0/sda0 43 p6_2 rxd0/scl0 44 p6_1 clk0 45 p6_0 rtcout cts0 / rts0 46 p13_7 47 p13_6 48 p13_5 49 p13_4 50 clkout p5_7 rdy
r01ds0031ej0210 rev.2.10 page 13 of 111 jul 31, 2012 m16c/65 group 1. overview table 1.8 pin names for the 128-pin package (2/3) pin no. control pin port i/o pin for peripheral function bus control pin interrupt timer serial interface a/d converter, d/a converter 51 p5_6 ale 52 p5_5 hold 53 p5_4 hlda 54 p13_3 55 p13_2 56 p13_1 57 p13_0 58 p5_3 bclk 59 p5_2 rd 60 p5_1 wrh / bhe 61 p5_0 wrl / wr 62 p12_7 63 p12_6 64 p12_5 65 p4_7 pwm1 txd7/sda7 cs3 66 p4_6 pwm0 rxd7/scl7 cs2 67 p4_5 clk7 cs1 68 p4_4 cts7 / rts7 cs0 69 p4_3 a19 70 p4_2 a18 71 p4_1 a17 72 p4_0 a16 73 p3_7 a15 74 p3_6 a14 75 p3_5 a13 76 p3_4 a12 77 p3_3 a11 78 p3_2 a10 79 p3_1 a9 80 p12_4 81 p12_3 82 p12_2 83 p12_1 84 p12_0 85 vcc2 86 p3_0 a8, [a8/d7] 87 vss 88 p2_7 an2_7 a7, [a7/d7], [a7/d6] 89 p2_6 an2_6 a6, [a6/d6], [a6/d5] 90 p2_5 int7 an2_5 a5, [a5/d5], [a5/d4] 91 p2_4 int6 an2_4 a4[a4/d4], [a4/d3] 92 p2_3 an2_3 a3, [a3/d3], [a3/d2] 93 p2_2 an2_2 a2, [a2/d2], [a2/d1] 94 p2_1 an2_1 a1, [a1/d1], [a1/d0] 95 p2_0 an2_0 a0, [a0/d0], a0 96 p1_7 int5 idu d15 97 p1_6 int4 idw d14 98 p1_5 int3 idv d13 99 p1_4 d12 100 p1_3 txd6/sda6 d11
r01ds0031ej0210 rev.2.10 page 14 of 111 jul 31, 2012 m16c/65 group 1. overview table 1.9 pin names for the 128-pin package (3/3) pin no. control pin port i/o pin for peripheral function bus control pin interrupt timer serial interface a/d converter, d/a converter 101 p1_2 rxd6/scl6 d10 102 p1_1 clk6 d9 103 p1_0 cts6 / rts6 d8 104 p0_7 an0_7 d7 105 p0_6 an0_6 d6 106 p0_5 an0_5 d5 107 p0_4 an0_4 d4 108 p0_3 an0_3 d3 109 p0_2 an0_2 d2 110 p0_1 an0_1 d1 111 p0_0 an0_0 d0 112 p11_7 113 p11_6 114 p11_5 115 p11_4 116 p11_3 117 p11_2 118 p11_1 119 p11_0 120 p10_7 ki3 an7 121 p10_6 ki2 an6 122 p10_5 ki1 an5 123 p10_4 ki0 an4 124 p10_3 an3 125 p10_2 an2 126 p10_1 an1 127 avss 128 p10_0 an0
r01ds0031ej0210 rev.2.10 page 15 of 111 jul 31, 2012 m16c/65 group 1. overview figure 1.6 pin assignment for the 100-pin package 56 55 54 53 52 51 1 m16c/65 group prqp0100jd-b (100p6f-a) (top view) 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 p0_0/an0_0/d0 p0_1/an0_1/d1 p0_2/an0_2/d2 p0_3/an0_3/d3 p0_4/an0_4/d4 p0_5/an0_5/d5 p0_6/an0_6/d6 p0_7/an0_7/d7 vref avss vcc1 xin xout vss reset cnvss p8_7/xcin p8_6/xcout byte p7_4/ta2out/w avcc p10_0/an0 p10_1/an1 p10_2/an2 p10_3/an3 p9_3/da0/tb3in/pwm0 p9_4/da1/tb4in/pwm1 p9_5/anex0/clk4 p9_6/anex1/sout4 p9_1/tb1in/pmc1/sin3 p9_2/tb2in/pmc0/sout3 p7_2/clk2/ta1out/v p8_2/int0 p7_1/rxd2/scl2/sclmm/ta0in/tb5in (1) p8_3/int1 p8_5/nmi/sd/cec (1) p9_7/adtrg/sin4 p9_0/tb0in/clk3 p7_0/txd2/sda2/sdamm/ta0out (1) p8_4/int2/zp p7_3/cts2/rts2/ta1in/v p7_5/ta2in/w p10_7/an7/ki3 p10_6/an6/ki2 p10_5/an5/ki1 p10_4/an4/ki0 p5_6/ale p5_5/hold p5_4/hlda p5_3/bclk p5_2/rd p5_7/rdy/clkout p6_3/txd0/sda0 p6_5/clk1 p6_6/rxd1/scl1 p6_7/txd1/sda1 p6_1/clk0 p6_2/rxd0/scl0 p6_0/rtcout/cts0/rts0 p6_4/cts1/rts1/cts0/clks1 p5_0/wrl/wr p5_1/wrh/bhe p1_4/d12 p3_1/a9 p3_2/a10 p3_3/a11 p3_4/a12 p3_5/a13 p3_6/a14 p3_7/a15 p4_0/a16 p4_1/a17 p4_2/a18 p4_3/a19 vcc2 vss p7_6/ta3out/txd5/sda5 p7_7/ta3in/clk5 p8_0/ta4out/u/rxd5/scl5 p8_1/ta4in/u/cts5/rts5 p1_0/cts6/rts6/d8 p1_1/clk6/d9 p1_2/rxd6/scl6/d10 p1_3/txd6/sda6/d11 p4_5/clk7/cs1 p4_4/cts7/rts7/cs0 p3_0/a8 [a8/d7] p2_0/an2_0/a0, [a0/d0], a0 p2_1/an2_1/a1, [a1/d1], [a1/d0] p2_2/an2_2/a2, [a2/d2], [a2/d1] p2_3/an2_3/a3, [a3/d3], [a3/d2] p2_4/int6/an2_4/a4, [a4/d4], [a4/d3] p2_5/int7/an2_5/a5, [a5/d5], [a5/d4] p2_7/an2_7/a7, [a7/d7], [a7/d6] see note 3 p2_6/an2_6/a6, [a6/d6], [a6/d5] p1_5/int3/idv/d13 p1_6/int4/idw/d14 p1_7/int5/idu/d15 p4_6/pwm0/rxd7/scl7/cs2 p4_7/pwm1/txd7/sda7/cs3 vcc2 ports vcc1 ports notes: 1. n-channel open drain output. 2. check the position of pin 1 by referring to appendix 1, package dimensions. 3. pin names in brackets [ ] r epresent a single functional signal. they should not be considered as two separate functional signals.
r01ds0031ej0210 rev.2.10 page 16 of 111 jul 31, 2012 m16c/65 group 1. overview figure 1.7 pin assignment for the 100-pin package 26 27 28 29 30 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 m16c/65 group plqp0100kb-a (100p6q-a) (top view) p0_0/an0_0/d0 p0_1/an0_1/d1 p0_2/an0_2/d2 p0_3/an0_3/d3 p0_4/an0_4/d4 p0_5/an0_5/d5 p0_6/an0_6/d6 p0_7/an0_7/d7 p1_0/cts6/rts6/d8 p1_1/clk6/d9 p1_2/rxd6/scl6/d10 vref avss avcc p10_0/an0 p10_1/an1 p10_2/an2 p10_3/an3 p9_5/anex0/clk4 p9_6/anex1/sout4 p9_7/adtrg/sin4 p10_7/an7/ki3 p10_6/an6/ki2 p10_5/an5/ki1 p10_4/an4/ki0 p1_3/txd6/sda6/d11 p1_4/d12 p3_1/a9 p3_2/a10 p3_3/a11 p3_4/a12 p3_5/a13 p3_6/a14 p3_7/a15 p4_0/a16 p4_1/a17 vcc2 vss p4_2/a18 p4_3/a19 p5_6/ale p5_5/hold p5_4/hlda p5_3/bclk p5_2/rd p5_7/rdy/clkout p6_3/txd0/sda0 p6_5/clk1 p6_6/rxd1/scl1 p6_7/txd1/sda1 p6_1/clk0 p6_2/rxd0/scl0 p6_0/rtcout/cts0/rts0 p6_4/cts1/rts1/cts0/clks1 p5_0/wrl/wr p5_1/wrh/bhe p7_2/clk2/ta1out/v p7_1/rxd2/scl2/sclmm/ta0in/tb5in (1) p7_0/txd2/sda2/sdamm/ta0out (1) vcc1 xin xout vss reset cnvss p8_7/xcin p8_6/xcout byte p7_4/ta2out/w p9_3/da0/tb3in/pwm0 p9_4/da1/tb4in/pwm1 p9_1/tb1in/pmc1/sin3 p9_2/tb2in/pmc0/sout3 p8_2/int0 p8_3/int1 p8_5/nmi/sd/cec (1) p9_0/tb0in/clk3 p8_4/int2/zp p7_5/ta2in/w p7_3/cts2/rts2/ta1in/v p7_6/ta3out/txd5/sda5 p7_7/ta3in/clk5 p8_0/ta4out/u/rxd5/scl5 p8_1/ta4in/u/cts5/rts5 p4_5/clk7/cs1 p4_4/cts7/rts7/cs0 p3_0/a8 [a8/d7] p2_0/an2_0/a0, [a0/d0], a0 p2_1/an2_1/a1, [a1/d1], [a1/d0] p2_2/an2_2/a2, [a2/d2], [a2/d1] p2_3/an2_3/a3, [a3/d3], [a3/d2] p2_4/int6/an2_4/a4, [a4/d4], [a4/d3] p2_5/int7/an2_5/a5, [a5/d5], [a5/d4] p2_6/an2_6/a6, [a6/d6], [a6/d5] p2_7/an2_7/a7, [a7/d7], [a7/d6] see note 3 p1_5/int3/idv/d13 p1_6/int4/idw/d14 p1_7/int5/idu/d15 p4_6/pwm0/rxd7/scl7/cs2 p4_7/pwm1/txd7/sda7/cs3 vcc2 ports vcc1 ports notes: 1. n-channel open drain output. 2. check the position of pin 1 by referring to appendix 1, package dimensions. 3. pin names in brackets [ ] represent a single functional signal. they should not be considered as two separate functional signals.
r01ds0031ej0210 rev.2.10 page 17 of 111 jul 31, 2012 m16c/65 group 1. overview table 1.10 pin names for the 100-pin package (1/2) pin no. control pin port i/o pin for peripheral function bus control pin fa fb interrupt timer serial interface a/d converter, d/a converter 1 99 p9_6 sout4 anex1 2 100 p9_5 clk4 anex0 3 1 p9_4 tb4in/pwm1 da1 4 2 p9_3 tb3in/pwm0 da0 5 3 p9_2 tb2in/pmc0 sout3 6 4 p9_1 tb1in/pmc1 sin3 7 5 p9_0 tb0in clk3 8 6 byte 97cnvss 10 8 xcin p8_7 11 9 xcout p8_6 12 10 reset 13 11 xout 14 12 vss 15 13 xin 16 14 vcc1 17 15 p8_5 nmi sd cec 18 16 p8_4 int2 zp 19 17 p8_3 int1 20 18 p8_2 int0 21 19 p8_1 ta4in/ ucts5 / rts5 22 20 p8_0 ta4out/u rxd5/scl5 23 21 p7_7 ta3in clk5 24 22 p7_6 ta3out txd5/sda5 25 23 p7_5 ta2in/ w 26 24 p7_4 ta2out/w 27 25 p7_3 ta1in/ vcts2 / rts2 28 26 p7_2 ta1out/v clk2 29 27 p7_1 ta0in/tb5in rxd2/scl2/sclmm 30 28 p7_0 ta0out txd2/sda2/sdamm 31 29 p6_7 txd1/sda1 32 30 p6_6 rxd1/scl1 33 31 p6_5 clk1 34 32 p6_4 cts1 / rts1 / cts0 / clks1 35 33 p6_3 txd0/sda0 36 34 p6_2 rxd0/scl0 37 35 p6_1 clk0 38 36 p6_0 rtcout cts0 / rts0 39 37 clkout p5_7 rdy 40 38 p5_6 ale 41 39 p5_5 hold 42 40 p5_4 hlda 43 41 p5_3 bclk 44 42 p5_2 rd 45 43 p5_1 wrh / bhe 46 44 p5_0 wrl / wr 47 45 p4_7 pwm1 txd7/sda7 cs3 48 46 p4_6 pwm0 rxd7/scl7 cs2 49 47 p4_5 clk7 cs1 50 48 p4_4 cts7 / rts7 cs0
r01ds0031ej0210 rev.2.10 page 18 of 111 jul 31, 2012 m16c/65 group 1. overview table 1.11 pin names for the 100-pin package (2/2) pin no. control pin port i/o pin for peripheral function bus control pin fa fb interrupt timer serial interface a/d converter, d/a converter 51 49 p4_3 a19 52 50 p4_2 a18 53 51 p4_1 a17 54 52 p4_0 a16 55 53 p3_7 a15 56 54 p3_6 a14 57 55 p3_5 a13 58 56 p3_4 a12 59 57 p3_3 a11 60 58 p3_2 a10 61 59 p3_1 a9 62 60 vcc2 63 61 p3_0 a8, [a8/d7] 64 62 vss 65 63 p2_7 an2_7 a7, [a7/d7], [a7/d6] 66 64 p2_6 an2_6 a6, [a6/d6], [a6/d5] 67 65 p2_5 int7 an2_5 a5, [a5/d5], [a5/d4] 68 66 p2_4 int6 an2_4 a4, [a4/d4], [a4/d3] 69 67 p2_3 an2_3 a3, [a3/d3], [a3/d2] 70 68 p2_2 an2_2 a2, [a2/d2], [a2/d1] 71 69 p2_1 an2_1 a1, [a1/d1], [a1/d0] 72 70 p2_0 an2_0 a0, [a0/d0], a0 73 71 p1_7 int5 idu d15 74 72 p1_6 int4 idw d14 75 73 p1_5 int3 idv d13 76 74 p1_4 d12 77 75 p1_3 txd6/sda6 d11 78 76 p1_2 rxd6/scl6 d10 79 77 p1_1 clk6 d9 80 78 p1_0 cts6 / rts6 d8 81 79 p0_7 an0_7 d7 82 80 p0_6 an0_6 d6 83 81 p0_5 an0_5 d5 84 82 p0_4 an0_4 d4 85 83 p0_3 an0_3 d3 86 84 p0_2 an0_2 d2 87 85 p0_1 an0_1 d1 88 86 p0_0 an0_0 d0 89 87 p10_7 ki3 an7 90 88 p10_6 ki2 an6 91 89 p10_5 ki1 an5 92 90 p10_4 ki0 an4 93 91 p10_3 an3 94 92 p10_2 an2 95 93 p10_1 an1 96 94 avss 97 95 p10_0 an0 98 96 vref 99 97 avcc 100 98 p9_7 sin4 adtrg
r01ds0031ej0210 rev.2.10 page 19 of 111 jul 31, 2012 m16c/65 group 1. overview 1.6 pin functions power supply: vcc2 is used to supply power to the external bus associated pins. the dual power supply configuration allows vcc2 to interface at a different voltage than vcc1. table 1.12 pin functions for the 128-pin package (1/3) signal name pin name i/o power supply description power supply input vcc1, vcc2, vss i- apply 2.7 to 5.5 v to pins vcc1 and vcc2 (vcc1 vcc2), and 0 v to the vss pin. analog power supply input avcc, avss i vcc1 this is the power supply for the a/d and d/a converters. connect the avcc pin to vcc1, and connect the avss pin to vss. reset input reset i vcc1 driving this pin low resets the mcu. cnvss cnvss i vcc1 input pin to switch processor mo des. after a reset, to start operating in single-chip mode, connect the cnvss pin to vss via a resistor. to start operating in microprocessor mode, connect the pin to vcc1. external data bus width select input byte i vcc1 input pin to select the data bus of the external area. the data bus is 16 bits when it is low and 8 bits when it is high. this pin must be fixed either high or low. connect the byte pin to vss in single-chip mode. bus control pins d0 to d7 i/o vcc2 inputs or outputs data (d0 to d7) while accessing an external area with a separate bus. d8 to d15 i/o vcc2 inputs or outputs data (d8 to d15) while accessing an external area with a 16-bit separate bus. a0 to a19 o vcc2 outputs address bits a0 to a19. a0/d0 to a7/d7 i/o vcc2 inputs or outputs data (d0 to d7) and outputs address bits (a0 to a7) by timesharing, while accessing an external area with an 8-bit multiplexed bus. a1/d0 to a8/d7 i/o vcc2 inputs or outputs data (d0 to d7) and outputs address bits (a1 to a8) by timesharing, while accessing an external area with a 16-bit multiplexed bus. cs0 to cs3 o vcc2 outputs chip-select signals cs0 to cs3 to specify an external area. wrl / wr wrh / bhe rd o vcc2 outputs wrl , wrh , ( wr , bhe ), and rd signals. wrl and wrh can be switched with bhe and wr . ? wrl , wrh , and rd selected if the external data bus is 16 bits, data is written to an even address in an external area when wrl is driven low. data is written to an odd address when wrh is driven low. data is read when rd is driven low. ? wr , bhe , and rd selected data is written to an external area when wr is driven low. data in an external area is read when rd is driven low. an odd address is accessed when bhe is driven low. select wr , bhe , and rd when using an 8-bit external data bus. ale o vcc2 outputs an ale signal to latch the address. hold i vcc2 hold input is unavailable. connect the hold pin to vcc2 via a resistor (pull-up). hlda o vcc2 in a hold state, hlda outputs a low-level signal. rdy i vcc2 the mcu bus is placed in wait state while the rdy pin is driven low.
r01ds0031ej0210 rev.2.10 page 20 of 111 jul 31, 2012 m16c/65 group 1. overview notes: 1. contact the manufacturer of crystal/ceramic reso nator regarding the oscillation characteristics. 2. txd2, sda2, and scl2 are n-channel open drain output pins. txdi (i = 0, 1, 5 to 7), sdai, and scli can be selected as cmos output pins or n-channel open drain output pins. table 1.13 pin functions for the 128-pin package (2/3) signal name pin name i/o power supply description main clock input xin i vcc1 i/o for the main clock osc illator. connect a ceramic resonator or crystal between pins xin and xout. (1) input an external clock to xin pin and leave xout pin open. main clock output xout o vcc1 sub clock input xcin i vcc1 i/o for a sub clock oscillator. connect a crystal between pins xcin and xcout. (1) input an external clock to xcin pin and leave xcout pin open. sub clock output xcout o vcc1 bclk output bclk o vcc2 outputs the bclk signal. clock output clkout o vcc2 outputs a clock with the same frequency as fc, f1, f8, or f32. int interrupt input int0 to int2 i vcc1 input for the int interrupt. int3 to int7 i vcc2 nmi interrupt input nmi i vcc1 input for the nmi interrupt. key input interrupt input ki0 to ki3 i vcc1 input for the key input interrupt. timer a ta0out to ta4out i/o vcc1 i/o for timers a0 to a4 (ta0out is n-channel open drain output). ta0in to ta4in i vcc1 input for timers a0 to a4. zp i vcc1 input for z-phase. timer b tb0in to tb5in i vcc1 input for timers b0 to b5. three-phase motor control timer u, u , v, v , w, w o vcc1 output for the three-phase motor control timer. sd i vcc1 forced cutoff input. idu, idv, idw i vcc2 input for the position data. real-time clock output rtcout o vcc1 output for the real-time clock. pwm output pwm0, pwm1 o vcc1, vcc2 pwm output. remote control signal receiver input pmc0, pmc1 i vcc1 input for the remote control signal receiver. serial interface uart0 to uart2, uart5 to uart7 cts0 to cts2 , cts5 i vcc1 input pins to control data transmission. cts6 , cts7 i vcc2 rts0 to rts2 , rts5 o vcc1 output pins to control data reception. rts6 , rts7 o vcc2 clk0 to clk2, clk5 i/o vcc1 transmit/receive clock i/o. clk6, clk7 i/o vcc2 rxd0 to rxd2, rxd5 i vcc1 serial data input. rxd6, rxd7 i vcc2 txd0 to txd2, txd5 o vcc1 serial data output. (2) txd6, txd7 o vcc2 clks1 o vcc1 output for the transmit/receive clock multiple-pin output function.
r01ds0031ej0210 rev.2.10 page 21 of 111 jul 31, 2012 m16c/65 group 1. overview table 1.14 pin functions for the 128-pin package (3/3) signal name pin name i/o p ower supply description uart0 to uart2, uart5 to uart7 i 2 c mode sda0 to sda2, sda5 i/o vcc1 serial data i/o. sda6, sda7 i/o vcc2 scl0 to scl2, scl5 i/o vcc1 transmit/receive clock i/o. scl6, scl7 i/o vcc2 serial interface si/o3, si/o4 clk3, clk4 i/o vcc1 transmit/receive clock i/o. sin3, sin4 i vcc1 serial data input. sout3, sout4 o vcc1 serial data output. multi-master i 2 c- bus interface sdamm i/o vcc1 serial data i/o (n-channel open drain output). sclmm i/o vcc1 transmit/receive clock i/o (n-channel open drain output). cec i/o cec i/o vcc1 cec i/o (n-channel open drain output). reference voltage input vref i vcc1 reference voltage input for the a/d and d/a converters. a/d converter an0 to an7 i vcc1 analog input. an0_0 to an0_7 an2_0 to an2_7 i vcc2 adtrg i vcc1 external trigger input. anex0, anex1 i vcc1 extended analog input. d/a converter da0, da1 o vcc1 output pin the d/a converter. i/o ports p0_0 to p0_7 p1_0 to p1_7 p2_0 to p2_7 p3_0 to p3_7 p4_0 to p4_7 p5_0 to p5_7 p12_0 to p12_7 p13_0 to p13_7 i/o vcc2 8-bit cmos i/o ports. a direction register determines whether each pin is used as an input port or an output port. a pull-up resistor may be enabled or disabled for input ports in 4-bit units. p6_0 to p6_7 p7_0 to p7_7 p8_0 to p8_7 p9_0 to p9_7 p10_0 to p10_7 p11_0 to p11_7 i/o vcc1 8-bit i/o ports having equivalent functions to p0. however, p7_0, p7_1, and p8_5 are n-channel open drain output ports. no pull-up resistor is provided. p8_5 is an input port for verifying the nmi pin level and shares a pin with nmi . p14_0, p14_1 i/o vcc1 i/o ports having equivalent functions to p0.
r01ds0031ej0210 rev.2.10 page 22 of 111 jul 31, 2012 m16c/65 group 1. overview power supply: vcc2 is used to supply power to the external bus associated pins. the dual power supply configuration allows vcc2 to interface at a different voltage than vcc1. table 1.15 pin functions for the 100-pin package (1/3) signal name pin name i/o power supply description power supply input vcc1, vcc2, vss i- apply 2.7 to 5.5 v to pins vcc1 and vcc2 (vcc1 vcc2) and 0 v to the vss pin. analog power supply input avcc, avss i vcc1 this is the power supply for the a/d and d/a converters. connect the avcc pin to vcc1, and connect the avss pin to vss. reset input reset i vcc1 driving this pin low resets the mcu. cnvss cnvss i vcc1 input pin to switch processor mo des. after a reset, to start operating in single-chip mode, connect the cnvss pin to vss via a resistor. to start operating in microprocessor mode, connect the pin to vcc1. external data bus width select input byte i vcc1 input pin to select the data bus of the external area. the data bus is 16 bits when it is low, and 8 bits when it is high. this pin must be fixed either high or low. connect the byte pin to vss in single-chip mode. bus control pins d0 to d7 i/o vcc2 inputs or outputs data (d0 to d7) while accessing an external area with a separate bus. d8 to d15 i/o vcc2 inputs or outputs data (d8 to d15) while accessing an external area with a 16-bit separate bus. a0 to a19 o vcc2 outputs address bits a0 to a19. a0/d0 to a7/d7 i/o vcc2 inputs or outputs data (d0 to d7) and outputs address bits (a0 to a7) by timesharing, while accessing an external area with an 8-bit multiplexed bus. a1/d0 to a8/d7 i/o vcc2 inputs or outputs data (d0 to d7) and outputs address bits (a1 to a8) by timesharing, while accessing an external area with a 16-bit multiplexed bus. cs0 to cs3 o vcc2 outputs chip-select signals cs0 to cs3 to specify an external area. wrl / wr wrh / bhe rd o vcc2 outputs wrl , wrh , ( wr , bhe ), and rd signals. wrl and wrh can be switched with bhe and wr . ? wrl , wrh , and rd selected if the external data bus is 16 bits, data is written to an even address in an external area when wrl is driven low. data is written to an odd address when wrh is driven low. data is read when rd is driven low. ? wr , bhe , and rd selected data is written to an external area when wr is driven low. data in an external area is read when rd is driven low. an odd address is accessed when bhe is driven low. select wr , bhe , and rd when using an 8-bit external data bus. ale o vcc2 outputs an ale signal to latch the address. hold i vcc2 hold input is unavailable. connect the hold pin to vcc2 via a resistor (pull-up). hlda o vcc2 in a hold state, hlda outputs a low-level signal. rdy i vcc2 the mcu bus is placed in a wait state while the rdy pin is driven low.
r01ds0031ej0210 rev.2.10 page 23 of 111 jul 31, 2012 m16c/65 group 1. overview notes: 1. contact the manufacturer of crystal/ceramic reso nator regarding the oscillation characteristics. 2. txd2, sda2, and scl2 are n-channel open drain output pins. txdi (i = 0, 1, 5 to 7), sdai, and scli can be selected as cmos output pins or n-channel open drain output pins. table 1.16 pin functions for the 100-pin package (2/3) signal name pin name i/o power supply description main clock input xin i vcc1 i/o for the main clock oscillator. connect a ceramic resonator or crystal between pins xin and xout. (1) input an external clock to xin pin and leave xout pin open. main clock output xout o vcc1 sub clock input xcin i vcc1 i/o for a sub clock oscillator. connect a crystal between xcin pin and xcout pin. (1) input an external clock to xcin pin and leave xcout pin open. sub clock output xcout o vcc1 bclk output bclk o vcc2 outputs the bclk signal. clock output clkout o vcc2 outputs a clock with the same frequency as fc, f1, f8, or f32. int interrupt input int0 to int2 i vcc1 input for the int interrupt. int3 to int7 i vcc2 nmi interrupt input nmi i vcc1 input for the nmi interrupt. key input interrupt input ki0 to ki3 i vcc1 input for the key input interrupt. timer a ta0out to ta4out i/o vcc1 i/o for timers a0 to a4 (ta0out is n-channel open drain output). ta0in to ta4in i vcc1 input for timers a0 to a4. zp i vcc1 input for z-phase. timer b tb0in to tb5in i vcc1 input for timers b0 to b5. three-phase motor control timer u, u , v, v , w, w o vcc1 output for the three-phase motor control timer. sd i vcc1 forced cutoff input. idu, idv, idw i vcc2 input for the position data. real-time clock output rtcout o vcc1 output for the real-time clock. pwm output pwm0, pwm1 o vcc1, vcc2 pwm output. remote control signal receiver input pmc0, pmc1 i vcc1 input for the remote control signal receiver. serial interface uart0 to uart2, uart5 to uart7 cts0 to cts2 , cts5 i vcc1 input pins to control data transmission. cts6 , cts7 i vcc2 rts0 to rts2 , rts5 o vcc1 output pins to control data reception. rts6 , rts7 o vcc2 clk0 to clk2, clk5 i/o vcc1 transmit/receive clock i/o. clk6, clk7 i/o vcc2 rxd0 to rxd2, rxd5 i vcc1 serial data input. rxd6, rxd7 i vcc2 txd0 to txd2, txd5 o vcc1 serial data output. (2) txd6, txd7 o vcc2 clks1 o vcc1 output for the transmit/receive clock multiple-pin output function.
r01ds0031ej0210 rev.2.10 page 24 of 111 jul 31, 2012 m16c/65 group 1. overview table 1.17 pin functions for the 100-pin package (3/3) signal name pin name i/o power supply description uart0 to uart2, uart5 to uart7 i 2 c mode sda0 to sda2, sda5 i/o vcc1 serial data i/o. sda6, sda7 i/o vcc2 scl0 to scl2, scl5 i/o vcc1 transmit/receive clock i/o. scl6, scl7 i/o vcc2 serial interface si/o3, si/o4 clk3, clk4 i/o vcc1 transmit/receive clock i/o. sin3, sin4 i vcc1 serial data input. sout3, sout4 o vcc1 serial data output. multi-master i 2 c-bus interface sdamm i/o vcc1 serial data i/o (n-channel open drain output). sclmm i/o vcc1 transmit/receive clock i/o (n-channel open drain output). cec i/o cec i/o vcc1 cec i/o (n-channel open drain output). reference voltage input vref i vcc1 reference voltage input for the a/d and d/a converters. a/d converter an0 to an7 i vcc1 analog input. an0_0 to an0_7 an2_0 to an2_7 ivcc2 adtrg i vcc1 external trigger input. anex0, anex1 i vcc1 extended analog input. d/a converter da0, da1 o vcc1 output for the d/a converter. i/o ports p0_0 to p0_7 p1_0 to p1_7 p2_0 to p2_7 p3_0 to p3_7 p4_0 to p4_7 p5_0 to p5_7 i/o vcc2 8-bit cmos i/o ports. a direction register determines whether each pin is used as an input port or an output port. a pull-up resistor may be enabled or disabled for input ports in 4-bit units. p6_0 to p6_7 p7_0 to p7_7 p8_0 to p8_7 p9_0 to p9_7 p10_0 to p10_7 i/o vcc1 8-bit i/o ports having equivalent functions to p0. however, p7_0, p7_1, and p8_5 are n-channel open drain output ports. no pull-up resistor is provided. p8_5 is an input port for verifying the nmi pin level and shares a pin with nmi .
r01ds0031ej0210 rev.2.10 page 25 of 111 jul 31, 2012 m16c/65 group 2. central processing unit (cpu) 2. central processi ng unit (cpu) figure 2.1 shows the cpu registers. seven registers (r0, r1, r2, r3, a0, a1, and fb) out of 13 compose a register bank, and there are two register banks. figure 2.1 cpu registers r0h (upper bits of r0) b15 b8 b7 b0 r3 intbh usp isp sb note: 1. these registers compose a register bank. there are two register banks. cdzsboiu ipl r2 b31 r3 r2 a1 a0 fb b19 intbl b15 b0 pc intbh is the 4 upper bits of the intb register and intbl is the 16 lower bits. b19 b0 b15 b0 flg b15 b0 b15 b0 b7 b8 data registers (1) address registers (1) frame base registers (1) program counter interrupt table register user stack pointer interrupt stack pointer static base register flag register reserved area carry flag debug flag zero flag sign flag register bank select flag overflow flag interrupt enable flag stack pointer select flag reserved area processor interrupt priority level r1h (upper bits of r1) r0l (lower bits of r0) r1l (lower bits of r1)
r01ds0031ej0210 rev.2.10 page 26 of 111 jul 31, 2012 m16c/65 group 2. central processing unit (cpu) 2.1 data registers (r 0, r1, r2, and r3) r0, r1, r2, and r3 are 16-bit registers used for transf er, arithmetic, and logic operations. r0 and r1 can be split into upper (r0h/r1h) and lower (r0l/r1l) bits to be used separately as 8-bit data registers. r0 can be combined with r2, and r3 can be combined with r1 and be used as 32-bit data registers r2r0 and r3r1, respectively. 2.2 address registers (a0 and a1) a0 and a1 are 16-bit registers used for indirect addre ssing, relative addressing, transfer, arithmetic, and logic operations. a0 can be combined with a1 and used as a 32-bit address register (a1a0). 2.3 frame base register (fb) fb is a 16-bit register that is used for fb relative addressing. 2.4 interrupt table register (intb) intb is a 20-bit register that indicates the star t address of a relocatable interrupt vector table. 2.5 program counter (pc) the pc is 20 bits wide and indicates the add ress of the next instruction to be executed. 2.6 user stack pointer (usp) and interrupt stack pointer (isp) the usp and isp stack pointers (sp) are each comprised of 16 bits. the u flag is used to switch between usp and isp. 2.7 static base register (sb) sb is a 16-bit register used for sb relative addressing. 2.8 flag register (flg) flg is an 11-bit register th at indicates the cpu state. 2.8.1 carry flag (c flag) the c flag retains a carry, borrow, or shift-out bit generated by the arithmetic/logic unit. 2.8.2 debug flag (d flag) the d flag is for debugging only. set it to 0. 2.8.3 zero flag (z flag) the z flag becomes 1 when an arithmetic opera tion results in 0. otherwise, it becomes 0. 2.8.4 sign flag (s flag) the s flag becomes 1 when an arithmetic operation re sults in a negative val ue. otherwise, it becomes 0. 2.8.5 register bank se lect flag (b flag) register bank 0 is selected when the b flag is 0. register bank 1 is selected when this flag is 1. 2.8.6 overflow flag (o flag) the o flag becomes 1 when an arithmetic operation re sults in an overflow. otherwise, it becomes 0.
r01ds0031ej0210 rev.2.10 page 27 of 111 jul 31, 2012 m16c/65 group 2. central processing unit (cpu) 2.8.7 interrupt enable flag (i flag) the i flag enables maskable interrupts. maskable interrupts are disabled when the i flag is 0, and enabled when it is 1. the i flag becomes 0 when an interrupt request is accepted. 2.8.8 stack pointer select flag (u flag) isp is selected when the u flag is 0. usp is selected when the u flag is 1. the u flag becomes 0 when a hardware interrupt request is accepted, or the int instruction of software interrupt number 0 to 31 is executed. 2.8.9 processor interrupt priority level (ipl) ipl is 3 bits wide and assigns processor interrupt priority levels from 0 to 7. if a requested interrupt has higher priority than ipl, the interrupt request is enabled. 2.8.10 reserved areas only set these bits to 0. the read value is undefined.
r01ds0031ej0210 rev.2.10 page 28 of 111 jul 31, 2012 m16c/65 group 3. address space 3. address space 3.1 address space the m16c/65 group has a 1 mb addre ss space from 00000h to fffffh. address space is expandable to 4 mb with the memory area expansion function. addres ses 40000h to bffffh can be used as external areas from bank 0 to bank 7. figure 3.1 shows the addr ess space. areas that can be accessed vary depending on processor mode and the status of each control bit. figure 3.1 address space bank 7 bank 6 bank 5 bank 4 bank 3 bank 2 bank 1 in 4 mb mode internal ram reserved area 00000h 0d000h sfr 00400h sfr 0d800h internal rom (data flash) 0e000h internal rom (program rom 2) 10000h reserved area internal rom (program rom 1) 14000h fffffh reserved area 28000h 27000h external area external area external area 40000h bffffh bank 0 04000h external area internal ram is allocated from address 00400h higher. program rom 1 is allocated from address fffffh lower. when data flash is enabled when program rom 2 is enabled memory expansion mode 1 mb address space 512 kb 8 notes: 1. do not access reserved areas. 2. the figure above applies under the following conditions: - the pm13 bit in the pm1 register is 0 (addresses 04000h to 0cfffh and 80000h to cffffh are us ed as external areas) - the iron bit in the prg2c register is 0 (addresses 40000h to 7ffffh are used as an external area) d0000h
r01ds0031ej0210 rev.2.10 page 29 of 111 jul 31, 2012 m16c/65 group 3. address space 3.2 memory map special function registers (sfrs) are allocated from address 00000h to 003ffh and from 0d000h to 0d7ffh. peripheral function control registers are loca ted here. all blank areas within sfrs are reserved. do not access these areas. internal ram is allocated from address 00400h and hi gher, with 10 kb of internal ram allocated from 00400h to 02bffh. internal ram is used not only fo r data storage, but also for the stack area when subroutines are called or when an interrupt request is accepted. the internal rom is flash memory. three internal rom areas are available: data flash, program rom 1, and program rom 2. the data flash is allocated from 0e000h to 0ffffh. this data flash area is mostly used for data storage, but can also store programs. program rom 2 is allocated from 10000h to 13fffh. program rom 1 is allocated from fffffh and lower, with the 64 kb program rom 1 area allocated from address f0000h to fffffh. the special page vectors are allocated from ffe00h to fffd7h. they are used for the jmps and jsrs instructions. refer to the m16c /60, m16c/20, m16c/tiny series software manual for details. the fixed vector table for interrupts is allocated from fffdch to fffffh. the 256 bytes beginning with the start address set in the intb register compose the relocatable vector table for interrupts. figure 3.2 shows the memory map. figure 3.2 memory map notes: 1. do not access reserved areas. 2. the figure above applies under the following conditions: - memory expansion mode - the pm10 bit in the pm1 register is 1 (addresses 0e000h to 0ffffh are used as data flash) - the prg2c0 bit in the prg2c register is 0 (program rom 2 enabled) - the pm13 bit in the pm1 register is 1 (all areas in internal ram, and the program rom 1 area from 80000h are usable) - the iron bit in the prg2c register is 1 (program rom 1 in addresses 40000h to 7ffffh enabled) 3. do not change the data from ffh. internal ram reserved area (1) 00000h xxxxxh 0d000h sfr 00400h 0d800h internal rom (data flash) 0e000h internal rom (program rom 2) 10000h reserved area (1) internal rom (program rom 1) 14000h 40000h yyyyyh fffffh reserved area (1) 28000h 27000h external area external area special page vector table fffffh fffdch ffe00h fffd8h reserved area (3) 256 bytes beginning with the start address set in the intb register fixed vector table address for id code stored ofs1 address relocatable vector table on-chip debugger monitor area 13fffh 13ff0h 13000h user boot code area size address yyyyyh program rom 1 e0000h 256 kb c0000h 384 kb a0000h 512 kb 640 kb 768 kb 80000h 60000h 40000h size address xxxxxh internal ram 12 kb 033ffh 20 kb 053ffh 31 kb 07fffh 47 kb 0bfffh 128 kb sfr external area
r01ds0031ej0210 rev.2.10 page 30 of 111 jul 31, 2012 m16c/65 group 3. address space 3.3 accessible area in each mode areas that can be accessed vary depending on processor mode and the status of each control bit. figure 3.3 shows the accessible area in each mode. in single-chip mode, the sfrs, internal ram, and internal rom can be accessed. in memory expansion mode, the sfrs, internal ram, internal rom, and external areas can be accessed. address space is expandable to 4 mb with the memory area expansion function. in microprocessor mode, the sfrs, internal ram, and external areas can be accessed. address space is expandable to 4 mb with the memory area expansion function. allocate rom to the fixed vector table from fffdch to fffffh. figure 3.3 accessible area in each mode notes: 1. do not access reserved areas. 2. the figure above applies under the following conditions: single-chip mode and memory expansion mode - the pm10 bit in the pm1 register is 1 (addresses 0e000h to 0ffffh are used as data flash) - the prg2c0 bit in the prg2c register is 0 (program rom 2 enabled) - the pm13 bit in the pm1 register is 1 (all areas in internal ram, and the program rom 1 area from 80000h are usable) - the iron bit in the prg2c register is 1 (program rom 1 in addresses 40000h to 7ffffh enabled) microprocessor mode - the pm10 bit is 0 (addresses 0e000h to 0ffffh are used as the cs2 area) - the prg2c0 bit is 1 (program rom 2 disabled) 00000h 0d000h 00400h 0d800h 0e000h 10000h 14000h fffffh 28000h 27000h 80000h 00000h 0d000h 00400h 0d800h 0e000h 10000h 14000h fffffh single-chip mode memory expansion mode 00000h 0d000h 00400h 0d800h fffffh 28000h 27000h microprocessor mode reserved area internal ram reserved area sfr sfr internal rom (data flash) internal rom (program rom 2) internal rom (program rom 1) reserved area reserved area external area external area internal ram reserved area sfr sfr internal rom (data flash) internal rom (program rom 2) reserved area internal rom (program rom 1) reserved area external area external area external area internal ram reserved area sfr sfr
r01ds0031ej0210 rev.2.10 page 31 of 111 jul 31, 2012 m16c/65 group 4. special function registers (sfrs) 4. special function registers (sfrs) 4.1 sfrs an sfr is a control register for a peripheral function. notes: 1. the blank areas are reserved. no access is allowed. 2. software reset, watchdog timer reset, oscillator stop detect reset, voltage monitor 1 reset, and voltage monitor 2 reset do not affect the following bits: bits pm01 and pm00 in the pm0 register. 3. oscillator stop detect reset does not affect bits cm20, cm21, and cm27. 4. the state of bits in the rstfr register depends on the reset type. 5. this is the reset value after hardware reset. refer to the explanation of each register for details. table 4.1 sfr information (1) (1) address register symbol reset value 0000h 0001h 0002h 0003h 0004h processor mode register 0 pm0 0000 0000b (cnvss pin is low) 0000 0011b (cnvss pin is high) (2) 0005h processor mode register 1 pm1 0000 1000b 0006h system clock control register 0 cm0 0100 1000b 0007h system clock control register 1 cm1 0010 0000b 0008h chip select control register csr 01h 0009h external area recovery cycle control register ewr xxxx xx00b 000ah protect register prcr 00h 000bh data bank register dbr 00h 000ch oscillation stop detection register cm2 0x00 0010b (3) 000dh 000eh 000fh 0010h program 2 area control register prg2c xxxx xx00b 0011h external area wait control expansion register ewc 00h 0012h peripheral clock select register pclkr 0000 0011b 0013h 0014h 0015h clock prescaler reset flag cpsrf 0xxx xxxxb 0016h 0017h 0018h reset source determine register rstfr xx00 001xb (hardware reset) (4) 0019h voltage detector 2 flag register vcr1 0000 1000b (5) 001ah voltage detector operation enable register vcr2 00h (5) 001bh chip select expansion control register cse 00h 001ch pll control register 0 plc0 0x01 x010b 001dh 001eh processor mode register 2 pm2 xx00 0x01b 001fh x: undefined
r01ds0031ej0210 rev.2.10 page 32 of 111 jul 31, 2012 m16c/65 group 4. special function registers (sfrs) notes: 1. the blank areas are reserved. no access is allowed. 2. this is the reset value after hardware reset. refer to the explanation of each register for details. table 4.2 sfr information (2) (1) address register symbol reset value 0020h 0021h 0022h 40 mhz on-chip oscillator co ntrol register 0 fra0 xxxx xx00b 0023h 0024h 0025h 0026h voltage monitor function select register vwce 00h 0027h 0028h voltage detector 1 level select register vd1ls 0000 1010b (2) 0029h 002ah voltage monitor 0 control register vw0c 1000 xx10b (2) 002bh voltage monitor 1 control register vw1c 1000 1010b (2) 002ch voltage monitor 2 control register vw2c 1000 0x10b (2) 002dh 002eh 002fh 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003ah 003bh 003ch 003dh 003eh 003fh x: undefined
r01ds0031ej0210 rev.2.10 page 33 of 111 jul 31, 2012 m16c/65 group 4. special function registers (sfrs) note: 1. the blank areas are reserved. no access is allowed. table 4.3 sfr information (3) (1) address register symbol reset value 0040h 0041h 0042h int7 interrupt control register int7ic xx00 x000b 0043h int6 interrupt control register int6ic xx00 x000b 0044h int3 interrupt control register int3ic xx00 x000b 0045h timer b5 interrupt control register tb5ic xxxx x000b 0046h timer b4 interrupt control register uart1 bus collision detection interrupt control register tb4ic u1bcnic xxxx x000b 0047h timer b3 interrupt control register uart0 bus collision detection interrupt control register tb3ic u0bcnic xxxx x000b 0048h si/o4 interrupt control register int5 interrupt control register s4ic int5ic xx00 x000b 0049h si/o3 interrupt control register int4 interrupt control register s3ic int4ic xx00 x000b 004ah uart2 bus collision detection interrupt control register bcnic xxxx x000b 004bh dma0 interrupt control register dm0ic xxxx x000b 004ch dma1 interrupt control register dm1ic xxxx x000b 004dh key input interrupt control register kupic xxxx x000b 004eh a/d conversion interrupt control register adic xxxx x000b 004fh uart2 transmit interrupt control register s2tic xxxx x000b 0050h uart2 receive interrupt control register s2ric xxxx x000b 0051h uart0 transmit interrupt control register s0tic xxxx x000b 0052h uart0 receive interrupt control register s0ric xxxx x000b 0053h uart1 transmit interrupt control register s1tic xxxx x000b 0054h uart1 receive interrupt control register s1ric xxxx x000b 0055h timer a0 interrupt control register ta0ic xxxx x000b 0056h timer a1 interrupt control register ta1ic xxxx x000b 0057h timer a2 interrupt control register ta2ic xxxx x000b 0058h timer a3 interrupt control register ta3ic xxxx x000b 0059h timer a4 interrupt control register ta4ic xxxx x000b 005ah timer b0 interrupt control register tb0ic xxxx x000b 005bh timer b1 interrupt control register tb1ic xxxx x000b 005ch timer b2 interrupt control register tb2ic xxxx x000b 005dh int0 interrupt control register int0ic xx00 x000b 005eh int1 interrupt control register int1ic xx00 x000b 005fh int2 interrupt control register int2ic xx00 x000b x: undefined
r01ds0031ej0210 rev.2.10 page 34 of 111 jul 31, 2012 m16c/65 group 4. special function registers (sfrs) note: 1. the blank areas are reserved. no access is allowed. table 4.4 sfr information (4) (1) address register symbol reset value 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h dma2 interrupt control register dm2ic xxxx x000b 006ah dma3 interrupt control register dm3ic xxxx x000b 006bh uart5 bus collision detection interrupt control register cec1 interrupt control register u5bcnic cec1ic xxxx x000b 006ch uart5 transmit interrupt control register cec2 interrupt control register s5tic cec2ic xxxx x000b 006dh uart5 receive interrupt control register s5ric xxxx x000b 006eh uart6 bus collision detection interrupt control register real-time clock periodic interrupt control register u6bcnic rtctic xxxx x000b 006fh uart6 transmit interrupt control register real-time clock compare interrupt control register s6tic rtccic xxxx x000b 0070h uart6 receive interrupt control register s6ric xxxx x000b 0071h uart7 bus collision detection interrupt control register remote control signal receiver 0 interrupt control register u7bcnic pmc0ic xxxx x000b 0072h uart7 transmit interrupt control register remote control signal receiver 1 interrupt control register s7tic pmc1ic xxxx x000b 0073h uart7 receive interrupt control register s7ric xxxx x000b 0074h 0075h 0076h 0077h 0078h 0079h 007ah 007bh i2c-bus interface interrupt control register iicic xxxx x000b 007ch scl/sda interrupt control register scldaic xxxx x000b 007dh 007eh 007fh 0080h to 017fh x: undefined
r01ds0031ej0210 rev.2.10 page 35 of 111 jul 31, 2012 m16c/65 group 4. special function registers (sfrs) note: 1. the blank areas are reserved. no access is allowed. table 4.5 sfr information (5) (1) address register symbol reset value 0180h dma0 source pointer sar0 xxh 0181h xxh 0182h 0xh 0183h 0184h dma0 destination pointer dar0 xxh 0185h xxh 0186h 0xh 0187h 0188h dma0 transfer counter tcr0 xxh 0189h xxh 018ah 018bh 018ch dma0 control register dm0con 0000 0x00b 018dh 018eh 018fh 0190h dma1 source pointer sar1 xxh 0191h xxh 0192h 0xh 0193h 0194h dma1 destination pointer dar1 xxh 0195h xxh 0196h 0xh 0197h 0198h dma1 transfer counter tcr1 xxh 0199h xxh 019ah 019bh 019ch dma1 control register dm1con 0000 0x00b 019dh 019eh 019fh 01a0h dma2 source pointer sar2 xxh 01a1h xxh 01a2h 0xh 01a3h 01a4h dma2 destination pointer dar2 xxh 01a5h xxh 01a6h 0xh 01a7h 01a8h dma2 transfer counter tcr2 xxh 01a9h xxh 01aah 01abh 01ach dma2 control register dm2con 0000 0x00b 01adh 01aeh 01afh x: undefined
r01ds0031ej0210 rev.2.10 page 36 of 111 jul 31, 2012 m16c/65 group 4. special function registers (sfrs) note: 1. the blank areas are reserved. no access is allowed. table 4.6 sfr information (6) (1) address register symbol reset value 01b0h dma3 source pointer sar3 xxh 01b1h xxh 01b2h 0xh 01b3h 01b4h dma3 destination pointer dar3 xxh 01b5h xxh 01b6h 0xh 01b7h 01b8h dma3 transfer counter tcr3 xxh 01b9h xxh 01bah 01bbh 01bch dma3 control register dm3con 0000 0x00b 01bdh 01beh 01bfh 01c0h timer b0-1 register tb01 xxh 01c1h xxh 01c2h timer b1-1 register tb11 xxh 01c3h xxh 01c4h timer b2-1 register tb21 xxh 01c5h xxh 01c6h pulse period/pulse width measurement mode function select register 1 ppwfs1 xxxx x000b 01c7h 01c8h timer b count source select register 0 tbcs0 00h 01c9h timer b count source select register 1 tbcs1 x0h 01cah 01cbh timer ab division control register 0 tckdivc0 0000 x000b 01cch 01cdh 01ceh 01cfh 01d0h timer a count source select register 0 tacs0 00h 01d1h timer a count source select register 1 tacs1 00h 01d2h timer a count source select register 2 tacs2 x0h 01d3h 01d4h 16-bit pulse width modulation mode func tion select register pwmfs 0xx0 x00xb 01d5h timer a waveform output function select register tapofs xxx0 0000b 01d6h 01d7h 01d8h timer a output waveform change enable register taow xxx0 x00xb 01d9h 01dah three-phase protect control register tprc 00h 01dbh 01dch 01ddh 01deh 01dfh x: undefined
r01ds0031ej0210 rev.2.10 page 37 of 111 jul 31, 2012 m16c/65 group 4. special function registers (sfrs) note: 1. the blank areas are reserved. no access is allowed. table 4.7 sfr information (7) (1) address register symbol reset value 01e0h timer b3-1 register tb31 xxh 01e1h xxh 01e2h timer b4-1 register tb41 xxh 01e3h xxh 01e4h timer b5-1 register tb51 xxh 01e5h xxh 01e6h pulse period/pulse width measurement mode function select reg- ister 2 ppwfs2 xxxx x000b 01e7h 01e8h timer b count source select register 2 tbcs2 00h 01e9h timer b count source select register 3 tbcs3 x0h 01eah 01ebh 01ech 01edh 01eeh 01efh 01f0h pmc0 function select register 0 pmc0con0 00h 01f1h pmc0 function select r egister 1 pmc0con1 00xx 0000b 01f2h pmc0 function select register 2 pmc0con2 0000 00x0b 01f3h pmc0 function select register 3 pmc0con3 00h 01f4h pmc0 status register pmc0sts 00h 01f5h pmc0 interrupt source select register pmc0int 00h 01f6h pmc0 compare control register pmc0cpc xxx0 x000b 01f7h pmc0 compare data register pmc0cpd 00h 01f8h pmc1 function select r egister 0 pmc1con0 xxx0 x000b 01f9h pmc1 function select r egister 1 pmc1con1 xxxx 0x00b 01fah pmc1 function select register 2 pmc1con2 0000 00x0b 01fbh pmc1 function select register 3 pmc1con3 00h 01fch pmc1 status register pmc1sts x000 x00xb 01fdh pmc1 interrupt source select register pmc1int x000 x00xb 01feh 01ffh 0200h 0201h 0202h 0203h 0204h 0205h interrupt source select register 3 ifsr3a 00h 0206h interrupt source select register 2 ifsr2a 00h 0207h interrupt source select register ifsr 00h 0208h 0209h 020ah 020bh 020ch 020dh 020eh address match interrupt enable register aier xxxx xx00b 020fh address match interrupt enab le register 2 aier2 xxxx xx00b x: undefined
r01ds0031ej0210 rev.2.10 page 38 of 111 jul 31, 2012 m16c/65 group 4. special function registers (sfrs) note: 1. the blank areas are reserved. no access is allowed. table 4.8 sfr information (8) (1) address register symbol reset value 0210h address match interrupt register 0 rmad0 00h 0211h 00h 0212h x0h 0213h 0214h address match interrupt register 1 rmad1 00h 0215h 00h 0216h x0h 0217h 0218h address match interrupt register 2 rmad2 00h 0219h 00h 021ah x0h 021bh 021ch address match interrupt register 3 rmad3 00h 021dh 00h 021eh x0h 021fh 0220h flash memory control register 0 fmr0 0000 0001b (other than user boot mode) 0010 0001b (user boot mode) 0221h flash memory control register 1 fmr1 00x0 xx0xb 0222h flash memory control register 2 fmr2 xxxx 0000b 0223h 0224h 0225h 0226h 0227h 0228h 0229h 022ah 022bh 022ch 022dh 022eh 022fh 0230h flash memory control register 6 fmr6 xx0x xx00b 0231h 0232h 0233h 0234h 0235h 0236h 0237h 0238h 0239h 023ah 023bh 023ch 023dh 023eh 023fh x: undefined
r01ds0031ej0210 rev.2.10 page 39 of 111 jul 31, 2012 m16c/65 group 4. special function registers (sfrs) note: 1. the blank areas are reserved. no access is allowed. table 4.9 sfr information (9) (1) address register symbol reset value 0240h 0241h 0242h 0243h 0244h uart0 special mode register 4 u0smr4 00h 0245h uart0 special mode register 3 u0smr3 000x 0x0xb 0246h uart0 special mode register 2 u0smr2 x000 0000b 0247h uart0 special mode register u0smr x000 0000b 0248h uart0 transmit/receive mode register u0mr 00h 0249h uart0 bit rate register u0brg xxh 024ah uart0 transmit buffer register u0tb xxh 024bh xxh 024ch uart0 transmit/receive control register 0 u0c0 0000 1000b 024dh uart0 transmit/receive control register 1 u0c1 00xx 0010b 024eh uart0 receive buffer register u0rb xxh 024fh xxh 0250h uart transmit/receive control register 2 ucon x000 0000b 0251h 0252h uart clock select register uclksel0 x0h 0253h 0254h uart1 special mode register 4 u1smr4 00h 0255h uart1 special mode register 3 u1smr3 000x 0x0xb 0256h uart1 special mode register 2 u1smr2 x000 0000b 0257h uart1 special mode register u1smr x000 0000b 0258h uart1 transmit/receive mode register u1mr 00h 0259h uart1 bit rate register u1brg xxh 025ah uart1 transmit buffer register u1tb xxh 025bh xxh 025ch uart1 transmit/receive control register 0 u1c0 0000 1000b 025dh uart1 transmit/receive control register 1 u1c1 00xx 0010b 025eh uart1 receive buffer register u1rb xxh 025fh xxh 0260h 0261h 0262h 0263h 0264h uart2 special mode register 4 u2smr4 00h 0265h uart2 special mode register 3 u2smr3 000x 0x0xb 0266h uart2 special mode register 2 u2smr2 x000 0000b 0267h uart2 special mode register u2smr x000 0000b 0268h uart2 transmit/receive mode register u2mr 00h 0269h uart2 bit rate register u2brg xxh 026ah uart2 transmit buffer register u2tb xxh 026bh xxh 026ch uart2 transmit/receive control register 0 u2c0 0000 1000b 026dh uart2 transmit/receive control register 1 u2c1 0000 0010b 026eh uart2 receive buffer register u2rb xxh 026fh xxh x: undefined
r01ds0031ej0210 rev.2.10 page 40 of 111 jul 31, 2012 m16c/65 group 4. special function registers (sfrs) note: 1. the blank areas are reserved. no access is allowed. table 4.10 sfr information (10) (1) address register symbol reset value 0270h si/o3 transmit/receive register s3trr xxh 0271h 0272h si/o3 control register s3c 0100 0000b 0273h si/o3 bit rate register s3brg xxh 0274h si/o4 transmit/receive register s4trr xxh 0275h 0276h si/o4 control register s4c 0100 0000b 0277h si/o4 bit rate register s4brg xxh 0278h si/o3, 4 control register 2 s34c2 00xx x0x0b 0279h 027ah 027bh 027ch 027dh 027eh 027fh 0280h 0281h 0282h 0283h 0284h uart5 special mode register 4 u5smr4 00h 0285h uart5 special mode register 3 u5smr3 000x 0x0xb 0286h uart5 special mode register 2 u5smr2 x000 0000b 0287h uart5 special mode register u5smr x000 0000b 0288h uart5 transmit/receive mode register u5mr 00h 0289h uart5 bit rate register u5brg xxh 028ah uart5 transmit buffer register u5tb xxh 028bh xxh 028ch uart5 transmit/receive control register 0 u5c0 0000 1000b 028dh uart5 transmit/receive control register 1 u5c1 0000 0010b 028eh uart5 receive buffer register u5rb xxh 028fh xxh 0290h 0291h 0292h 0293h 0294h uart6 special mode register 4 u6smr4 00h 0295h uart6 special mode register 3 u6smr3 000x 0x0xb 0296h uart6 special mode register 2 u6smr2 x000 0000b 0297h uart6 special mode register u6smr x000 0000b 0298h uart6 transmit/receive mode register u6mr 00h 0299h uart6 bit rate register u6brg xxh 029ah uart6 transmit buffer register u6tb xxh 029bh xxh 029ch uart6 transmit/receive control register 0 u6c0 0000 1000b 029dh uart6 transmit/receive control register 1 u6c1 0000 0010b 029eh uart6 receive buffer register u6rb xxh 029fh xxh x: undefined
r01ds0031ej0210 rev.2.10 page 41 of 111 jul 31, 2012 m16c/65 group 4. special function registers (sfrs) note: 1. the blank areas are reserved. no access is allowed. table 4.11 sfr information (11) (1) address register symbol reset value 02a0h 02a1h 02a2h 02a3h 02a4h uart7 special mode register 4 u7smr4 00h 02a5h uart7 special mode register 3 u7smr3 000x 0x0xb 02a6h uart7 special mode register 2 u7smr2 x000 0000b 02a7h uart7 special mode register u7smr x000 0000b 02a8h uart7 transmit/receive mode register u7mr 00h 02a9h uart7 bit rate register u7brg xxh 02aah uart7 transmit buffer register u7tb xxh 02abh xxh 02ach uart7 transmit/receive control register 0 u7c0 0000 1000b 02adh uart7 transmit/receive control register 1 u7c1 0000 0010b 02aeh uart7 receive buffer register u7rb xxh 02afh xxh 02b0h i2c0 data shift register s00 xxh 02b1h 02b2h i2c0 address regi ster 0 s0d0 0000 000xb 02b3h i2c0 control register 0 s1d0 00h 02b4h i2c0 clock control register s20 00h 02b5h i2c0 start/stop condition control register s2d0 0001 1010b 02b6h i2c0 control register 1 s3d0 0011 0000b 02b7h i2c0 control register 2 s4d0 00h 02b8h i2c0 status register 0 s10 0001 000xb 02b9h i2c0 status register 1 s11 xxxx x000b 02bah i2c0 address register 1 s0d1 0000 000xb 02bbh i2c0 address register 2 s0d2 0000 000xb 02bch 02bdh 02beh 02bfh 02c0h to 02ffh x: undefined
r01ds0031ej0210 rev.2.10 page 42 of 111 jul 31, 2012 m16c/65 group 4. special function registers (sfrs) note: 1. the blank areas are reserved. no access is allowed. table 4.12 sfr information (12) (1) address register symbol reset value 0300h timer b3/b4/b5 count start flag tbsr 000x xxxxb 0301h 0302h timer a1-1 register ta11 xxh 0303h xxh 0304h timer a2-1 register ta21 xxh 0305h xxh 0306h timer a4-1 register ta41 xxh 0307h xxh 0308h three-phase pwm control register 0 invc0 00h 0309h three-phase pwm control register 1 invc1 00h 030ah three-phase output buffer register 0 idb0 xx11 1111b 030bh three-phase output buffer register 1 idb1 xx11 1111b 030ch dead time timer dtt xxh 030dh timer b2 interrupt generati on frequency set counter ictb2 xxh 030eh position-data-retain function control register pdrf xxxx 0000b 030fh 0310h timer b3 register tb3 xxh 0311h xxh 0312h timer b4 register tb4 xxh 0313h xxh 0314h timer b5 register tb5 xxh 0315h xxh 0316h 0317h 0318h port function control register pfcr 0011 1111b 0319h 031ah 031bh timer b3 mode register tb3mr 00xx 0000b 031ch timer b4 mode register tb4mr 00xx 0000b 031dh timer b5 mode register tb5mr 00xx 0000b 031eh 031fh 0320h count start flag tabsr 00h 0321h 0322h one-shot start flag onsf 00h 0323h trigger select register trgsr 00h 0324h increment/decrement flag udf 00h 0325h 0326h timer a0 register ta0 xxh 0327h xxh 0328h timer a1 register ta1 xxh 0329h xxh 032ah timer a2 register ta2 xxh 032bh xxh 032ch timer a3 register ta3 xxh 032dh xxh 032eh timer a4 register ta4 xxh 032fh xxh x: undefined
r01ds0031ej0210 rev.2.10 page 43 of 111 jul 31, 2012 m16c/65 group 4. special function registers (sfrs) note: 1. the blank areas are reserved. no access is allowed. table 4.13 sfr information (13) (1) address register symbol reset value 0330h timer b0 register tb0 xxh 0331h xxh 0332h timer b1 register tb1 xxh 0333h xxh 0334h timer b2 register tb2 xxh 0335h xxh 0336h timer a0 mode register ta0mr 00h 0337h timer a1 mode register ta1mr 00h 0338h timer a2 mode register ta2mr 00h 0339h timer a3 mode register ta3mr 00h 033ah timer a4 mode register ta4mr 00h 033bh timer b0 mode register tb0mr 00xx 0000b 033ch timer b1 mode register tb1mr 00xx 0000b 033dh timer b2 mode register tb2mr 00xx 0000b 033eh timer b2 special mode register tb2sc x000 0000b 033fh 0340h real-time clock second data register rtcsec 00h 0341h real-time clock minute data register rtcmin x000 0000b 0342h real-time clock hour data register rtchr xx00 0000b 0343h real-time clock day data register rtcwk xxxx x000b 0344h real-time clock control register 1 rtccr1 0000 x00xb 0345h real-time clock control register 2 rtccr2 x000 0000b 0346h real-time clock count source select register rtccsr xxx0 0000b 0347h 0348h real-time clock second compare data register rtccsec x000 0000b 0349h real-time clock minute compare data register rtccmin x000 0000b 034ah real-time clock hour compare data register rtcchr x000 0000b 034bh 034ch 034dh 034eh 034fh 0350h cec function control register 1 cecc1 xxxx x000b 0351h cec function control register 2 cecc2 00h 0352h cec function control register 3 cecc3 xxxx 0000b 0353h cec function control register 4 cecc4 00h 0354h cec flag register cecflg 00h 0355h cec interrupt source select register cisel 00h 0356h cec transmit buffer register 1 cctb1 00h 0357h cec transmit buffer register 2 cctb2 xxxx xx00b 0358h cec receive buffer register 1 ccrb1 00h 0359h cec receive buffer register 2 ccrb2 xxxx x000b 035ah cec receive follower address set register 1 cradri1 00h 035bh cec receive follower address set register 2 cradri2 00h 035ch 035dh 035eh 035fh x: undefined
r01ds0031ej0210 rev.2.10 page 44 of 111 jul 31, 2012 m16c/65 group 4. special function registers (sfrs) notes: 1. the blank areas are reserved. no access is allowed. 2. values after hardware reset, power-on rese t, or voltage monitor 0 reset are as follows: - 00000000b when a low-level signal is input to the cnvss pin - 00000010b when a high-level signal is input to the cnvss pin values after voltage monitor 1 reset, voltage monitor 2 reset, software reset, watchdog timer reset, or oscillation stop detect reset are as follows: - 00000000b when bits pm01 and pm00 in the pm0 register are 00b (single-chip mode). - 00000010b when bits pm01 and pm00 in the pm0 register are 01b (memory expansion mode) or 11b (microprocessor mode). 3. when the csproini bit in the ofs1 address is 0, the reset value is 1000 0000b. table 4.14 sfr information (14) (1) address register symbol reset value 0360h pull-up control register 0 pur0 00h 0361h pull-up control register 1 pur1 0000 0000b (2) 0000 0010b 0362h pull-up control register 2 pur2 00h 0363h pull-up control register 3 pur3 00h 0364h 0365h 0366h port control register pcr 0000 0xx0b 0367h 0368h 0369h nmi/sd digital filter register nmidf xxxx x000b 036ah 036bh 036ch 036dh 036eh 036fh 0370h pwm control register 0 pwmcon0 00h 0371h 0372h pwm0 prescaler pwmpre0 00h 0373h pwm0 register pwmreg0 00h 0374h pwm1 prescaler pwmpre1 00h 0375h pwm1 register pwmreg1 00h 0376h pwm control register 1 pwmcon1 00h 0377h 0378h 0379h 037ah 037bh 037ch count source protection mode register cspr 00h (3) 037dh watchdog timer refresh register wdtr xxh 037eh watchdog timer start register wdts xxh 037fh watchdog timer control register wdc 00xx xxxxb 0380h to 038fh x: undefined
r01ds0031ej0210 rev.2.10 page 45 of 111 jul 31, 2012 m16c/65 group 4. special function registers (sfrs) note: 1. the blank areas are reserved. no access is allowed. table 4.15 sfr information (15) (1) address register symbol reset value 0390h dma2 source select register dm2sl 00h 0391h 0392h dma3 source select register dm3sl 00h 0393h 0394h 0395h 0396h 0397h 0398h dma0 source select register dm0sl 00h 0399h 039ah dma1 source select register dm1sl 00h 039bh 039ch 039dh 039eh 039fh 03a0h 03a1h 03a2h open-circuit detection assist function register ainrst xx00 xxxxb 03a3h 03a4h 03a5h 03a6h 03a7h 03a8h 03a9h 03aah 03abh 03ach 03adh 03aeh 03afh 03b0h 03b1h 03b2h 03b3h 03b4h sfr snoop address register crcsar xxxx xxxxb 03b5h 00xx xxxxb 03b6h crc mode register crcmr 0xxx xxx0b 03b7h 03b8h 03b9h 03bah 03bbh 03bch crc data register crcd xxh 03bdh xxh 03beh crc input register crcin xxh 03bfh x: undefined
r01ds0031ej0210 rev.2.10 page 46 of 111 jul 31, 2012 m16c/65 group 4. special function registers (sfrs) note: 1. the blank areas are reserved. no access is allowed. table 4.16 sfr information (16) (1) address register symbol reset value 03c0h a/d register 0 ad0 xxxx xxxxb 03c1h 0000 00xxb 03c2h a/d register 1 ad1 xxxx xxxxb 03c3h 0000 00xxb 03c4h a/d register 2 ad2 xxxx xxxxb 03c5h 0000 00xxb 03c6h a/d register 3 ad3 xxxx xxxxb 03c7h 0000 00xxb 03c8h a/d register 4 ad4 xxxx xxxxb 03c9h 0000 00xxb 03cah a/d register 5 ad5 xxxx xxxxb 03cbh 0000 00xxb 03cch a/d register 6 ad6 xxxx xxxxb 03cdh 0000 00xxb 03ceh a/d register 7 ad7 xxxx xxxxb 03cfh 0000 00xxb 03d0h 03d1h 03d2h 03d3h 03d4h a/d control register 2 adcon2 0000 x00xb 03d5h 03d6h a/d control register 0 adcon0 0000 0xxxb 03d7h a/d control register 1 adcon1 0000 x000b 03d8h d/a0 register da0 00h 03d9h 03dah d/a1 register da1 00h 03dbh 03dch d/a control register dacon 00h 03ddh 03deh 03dfh 03e0h port p0 register p0 xxh 03e1h port p1 register p1 xxh 03e2h port p0 direction register pd0 00h 03e3h port p1 direction register pd1 00h 03e4h port p2 register p2 xxh 03e5h port p3 register p3 xxh 03e6h port p2 direction register pd2 00h 03e7h port p3 direction register pd3 00h 03e8h port p4 register p4 xxh 03e9h port p5 register p5 xxh 03eah port p4 direction register pd4 00h 03ebh port p5 direction register pd5 00h 03ech port p6 register p6 xxh 03edh port p7 register p7 xxh 03eeh port p6 direction register pd6 00h 03efh port p7 direction register pd7 00h x: undefined
r01ds0031ej0210 rev.2.10 page 47 of 111 jul 31, 2012 m16c/65 group 4. special function registers (sfrs) note: 1. the blank areas are reserved. no access is allowed. table 4.17 sfr information (17) (1) address register symbol reset value 03f0h port p8 register p8 xxh 03f1h port p9 register p9 xxh 03f2h port p8 direction register pd8 00h 03f3h port p9 direction register pd9 00h 03f4h port p10 register p10 xxh 03f5h port p11 register p11 xxh 03f6h port p10 direction register pd10 00h 03f7h port p11 direction register pd11 00h 03f8h port p12 register p12 xxh 03f9h port p13 register p13 xxh 03fah port p12 direction register pd12 00h 03fbh port p13 direction register pd13 00h 03fch port p14 register p14 xxh 03fdh 03feh port p14 direction register pd14 xxxx xx00b 03ffh x: undefined
r01ds0031ej0210 rev.2.10 page 48 of 111 jul 31, 2012 m16c/65 group 4. special function registers (sfrs) note: 1. the blank areas are reserved. no access is allowed. table 4.18 sfr information (18) (1) address register symbol reset value d080h pmc0 header pattern set register (min) pmc0hdpmin 0000 0000b d081h xxxx x000b d082h pmc0 header pattern set register (max) pmc0hdpmax 0000 0000b d083h xxxx x000b d084h pmc0 data 0 pattern set register (min) pmc0d0pmin 00h d085h pmc0 data 0 pattern set register (max) pmc0d0pmax 00h d086h pmc0 data 1 pattern set register (min) pmc0d1pmin 00h d087h pmc0 data 1 pattern set register (max) pmc0d1pmax 00h d088h pmc0 measurements register pmc0tim 00h d089h 00h d08ah d08bh d08ch pmc0 receive data store register 0 pmc0dat0 00h d08dh pmc0 receive data store register 1 pmc0dat1 00h d08eh pmc0 receive data store register 2 pmc0dat2 00h d08fh pmc0 receive data store register 3 pmc0dat3 00h d090h pmc0 receive data store register 4 pmc0dat4 00h d091h pmc0 receive data store register 5 pmc0dat5 00h d092h pmc0 receive bit count register pmc0rbit xx00 0000b d093h d094h pmc1 header pattern set register (min) pmc1hdpmin 0000 0000b d095h xxxx x000b d096h pmc1 header pattern set register (max) pmc1hdpmax 0000 0000b d097h xxxx x000b d098h pmc1 data 0 pattern set register (min) pmc1d0pmin 00h d099h pmc1 data 0 pattern set register (max) pmc1d0pmax 00h d09ah pmc1 data 1 pattern set register (min) pmc1d1pmin 00h d09bh pmc1 data 1 pattern set register (max) pmc1d1pmax 00h d09ch pmc1 measurements register pmc1tim 00h d09dh 00h d09eh d09fh x: undefined
r01ds0031ej0210 rev.2.10 page 49 of 111 jul 31, 2012 m16c/65 group 4. special function registers (sfrs) 4.2 notes on sfrs 4.2.1 register settings table 4.19 lists registers with write-only bits a nd registers whose function differs between reading and writing. set these registers with immediate values. do not use read-modify- write instructions. when establishing the next value by altering the existing value, write the existing value to the ram as well as to the register. transfer the next value to the register after making changes in the ram. read-modify-write instructions can be used when writing to the no register bits. table 4.19 registers with write-only bits address register symbol 0249h uart0 bit rate register u0brg 024bh to 024ah uart0 transmit buffer register u0tb 0259h uart1 bit rate register u1brg 025bh to 025ah uart1 transmit buffer register u1tb 0269h uart2 bit rate register u2brg 026bh to 026ah uart2 transmit buffer register u2tb 0273h si/o3 bit rate register s3brg 0277h si/o4 bit rate register s4brg 0289h uart5 bit rate register u5brg 028bh to 028ah uart5 transmit buffer register u5tb 0299h uart6 bit rate register u6brg 029bh to 029ah uart6 transmit buffer register u6tb 02a9h uart7 bit rate register u7brg 02abh to 02aah uart7 transmit buffer register u7tb 02b6h i2c0 control register 1 s3d0 02b8h i2c0 status register 0 s10 0303h to 0302h timer a1-1 register ta11 0305h to 0304h timer a2-1 register ta21 0307h to 0306h timer a4-1 register ta41 030ah three-phase output buffer register 0 idb0 030bh three-phase output buffer register 1 idb1 030ch dead time timer dtt 030dh timer b2 interrupt generation frequency set counter ictb2 0327h to 0326h timer a0 register ta0 0329h to 0328h timer a1 register ta1 032bh to 032ah timer a2 register ta2 032dh to 032ch timer a3 register ta3 032fh to 032eh timer a4 register ta4 037dh watchdog timer refresh register wdtr 037eh watchdog timer start register wdts
r01ds0031ej0210 rev.2.10 page 50 of 111 jul 31, 2012 m16c/65 group 4. special function registers (sfrs) table 4.20 read-modify-write instructions function mnemonic transfer mov dir bit processing bclr, bm cnd , bnot, bset, btstc, and btsts shifting rolc, rorc, rot, sha, and shl arithmetic operation abs, adc, adcf, add, dec, div, divu, divx, exts, inc, mul, mulu, neg, sbb, and sub decimal operation dadc, dadd, dsbb, and dsub logical operation and, not, or, and xor jump adjnz, sbjnz
r01ds0031ej0210 rev.2.10 page 51 of 111 jul 31, 2012 m16c/65 group 5. electrical characteristics 5. electrical characteristics 5.1 electrical characteristi cs (common to 3 v and 5 v) 5.1.1 absolute maximum rating note: 1. maximum value is 6.5 v. table 5.1 absolute maximum ratings symbol parameter condition rated value unit v cc1 supply voltage v cc1 = av cc ? 0.3 to 6.5 v v cc2 supply voltage v cc1 = av cc ? 0.3 to v cc1 + 0.1 (1) v av cc analog supply voltage v cc1 = av cc ? 0.3 to 6.5 v v ref analog reference voltage v cc1 = av cc ? 0.3 to v cc1 + 0.1 (1) v v i input voltage reset , cnvss, byte, p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_7, p14_0, p14_1 xin ? 0.3 to v cc1 + 0.3 (1) v p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p12_0 to p12_7, p13_0 to p13_7 ? 0.3 to v cc2 + 0.3 (1) v p7_0, p7_1, p8_5 ? 0.3 to 6.5 v v o output voltage p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_7, p14_0, p14_1 xout ? 0.3 to v cc1 + 0.3 (1) v p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p12_0 to p12_7, p13_0 to p13_7 ? 0.3 to v cc2 + 0.3 (1) v p7_0, p7_1, p8_5 ? 0.3 to 6.5 v p d power consumption ? 40 c < t opr 85 c 300 mw t opr operating temperature when the mcu is operating ? 20 to 85/ ? 40 to 85 c flash program erase program area 0 to 60 data area ? 20 to 85/ ? 40 to 85 t stg storage temperature ? 65 to 150 c
r01ds0031ej0210 rev.2.10 page 52 of 111 jul 31, 2012 m16c/65 group 5. electrical characteristics 5.1.2 recommended operating conditions note: 1. the average output current is the mean value within 100 ms. table 5.2 recommended operating conditions (1/3) v cc1 = v cc2 = 2.7 to 5.5 v at t opr = -20 c to 85 c/-40 c to 85 c unless otherwise specified. symbol parameter standard unit min. typ. max. v cc1 , v cc2 supply voltage (v cc1 v cc2 ) cec function is not used 2.7 5.0 5.5 v cec function is used 2.7 3.63 v av cc analog supply voltage v cc1 v v ss supply voltage 0 v av ss analog supply voltage 0 v v ih high input voltage p3_1 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p12_0 to p12_7, p13_0 to p13_7 0.8v cc2 v cc2 v p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 (in single-chip mode) 0.8v cc2 v cc2 v p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 ( data input in memory expansion and microprocessor modes ) 0.5v cc2 v cc2 v p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_7, p14_0, p14_1 xin, reset , cnvss, byte 0.8v cc1 v cc1 v p7_0, p7_1, p8_5 0.8v cc1 6.5 v cec 0.7v cc1 v v il low input voltage p3_1 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p12_0 to p12_7, p13_0 to p13_7 00.2v cc2 v p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 (in single-chip mode) 00 . 2 v cc2 v p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 ( data input in memory expansion and microprocessor mode ) 0 0.16v cc2 v p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_7, p9_0 to p9_7, p10_0 to p10_7,p11_0 to p11_7, p14_0, p14_1 xin, reset , cnvss, byte 00 . 2 v cc1 v cec 0.26v cc1 v i oh(sum) high peak output current sum of i oh(peak) at p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7 -40.0 ma sum of i oh(peak) at p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p12_0 to p12_7, and p13_0 to p13_7 -40.0 ma sum of i oh(peak) at p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_4 -40.0 ma sum of i oh(peak) at p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_7, p14_0 to p14_1 -40.0 ma i oh(peak) high peak output current p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_7, p12_0 to p12_7, p13_0 to p13_7, p14_0, p14_1 ? 10.0 ma i oh(avg) high average output current (1) p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_7, p12_0 to p12_7, p13_0 to p13_7, p14_0, p14_1 ? 5.0 ma
r01ds0031ej0210 rev.2.10 page 53 of 111 jul 31, 2012 m16c/65 group 5. electrical characteristics note: 1. the average output current is the mean value within 100 ms. table 5.3 recommended operating conditions (2/3) v cc1 = v cc2 = 2.7 to 5.5 v at t opr = -20 c to 85 c/-40 c to 85 c unless otherwise specified. symbol parameter standard unit min. typ. max. i ol(sum) low peak output current sum of i ol(peak) at p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_7, p14_0 to p14_1 80.0 ma sum of i ol(peak) at p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_5, p12_0 to p12_7, p13_0 to p13_7 80.0 ma i ol(peak) low peak output current p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_7, p12_0 to p12_7, p13_0 to p13_7, p14_0, p14_1 10.0 ma i ol(avg) low average output current (1) p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_7, p12_0 to p12_7, p13_0 to p13_7, p14_0, p14_1 5.0 ma f (xin) main clock input oscillation frequency v cc1 = 2.7 v to 5.5 v 2 20 mhz f (xcin) sub clock oscillation frequency 32.768 50 khz f (pll) pll clock oscillation frequency v cc1 = 2.7 v to 5.5 v 10 32 mhz f (bclk) cpu operation clock 2 32 mhz t su(pll) pll frequency synthesizer stabilization wait time v cc1 = 5.0 v 2 ms v cc1 = 3.0 v 3 ms
r01ds0031ej0210 rev.2.10 page 54 of 111 jul 31, 2012 m16c/65 group 5. electrical characteristics note: 1. the device is operationally guaranteed under these operating conditions. figure 5.1 ripple waveform table 5.4 recommended operating conditions (3/3) (1) v cc1 = 2.7 to 5.5 v, v ss = 0 v, and t opr = -20 c to 85 c/-40 c to 85 c unless otherwise specified. the ripple voltage must not exceed v r(vcc1) and/or dv r(vcc1) /dt. symbol parameter standard unit min. typ. max. v r(vcc1) allowable ripple voltage v cc1 = 5.0 v 0.5 vp-p v cc1 = 3.0 v 0.3 vp-p dv r(vcc1) /dt ripple voltage falling gradient v cc1 = 5.0 v 0.3 v/ms v cc1 = 3.0 v 0.3 v/ms v r( ) v cc1 v cc1
r01ds0031ej0210 rev.2.10 page 55 of 111 jul 31, 2012 m16c/65 group 5. electrical characteristics 5.1.3 a/d conversion characteristics notes: 1. use when av cc = v cc1 . 2. flash memory rewrite disabled. except for the analog input pin, set the pins to be measured as input ports and connect them to v ss . see figure 5.2 ?a/d accuracy measure circuit?. figure 5.2 a/d accuracy measure circuit table 5.5 a/d conversion characteristics (1/2) (1) v cc1 = av cc = 3.0 to 5.5 v v cc2 v ref , v ss = av ss = 0 v at t opr = -20 c to 85 c/-40 c to 85 c unless otherwise specified. symbol parameter measuring condition standard unit min. typ. max. -r e s o l u t i o n a v cc = v cc1 v cc2 v ref 10 bits i nl integral non-linearity error 10 bits v cc1 = 5.0 v an0 to an7 input, an0_0 to an0_7 input, an2_0 to an2_7 input, anex0, anex1 input (note 2) 3 lsb v cc1 = 3.3 v an0 to an7 input, an0_0 to an0_7 input, an2_0 to an2_7 input, anex0, anex1 input (note 2) 3 lsb v cc1 = 3.0 v an0 to an7 input, an0_0 to an0_7 input, an2_0 to an2_7 input, anex0, anex1 input (note 2) 3 lsb - absolute accuracy 10 bits v cc1 = 5.0 v an0 to an7 input, an0_0 to an0_7 input, an2_0 to an2_7 input, anex0, anex1 input (note 2) 3 lsb v cc1 = 3.3 v an0 to an7 input, an0_0 to an0_7 input, an2_0 to an2_7 input, anex0, anex1 input (note 2) 3 lsb v cc1 = 3.0 v an0 to an7 input, an0_0 to an0_7 input, an2_0 to an2_7 input, anex0, anex1 input (note 2) 3 lsb an analog input an: one of the analog input pin p0 to p14: i/o pins other than an p0 to p14
r01ds0031ej0210 rev.2.10 page 56 of 111 jul 31, 2012 m16c/65 group 5. electrical characteristics notes: 1. use when av cc = v cc1 . 2. when v cc1 v cc2 , set as below: analog input voltage (an0 to an7, anex0, and anex1) v cc1 analog input voltage (an0_0 to an0_7 and an2_0 to an2_7) v cc2 . 3. when analog input voltage is over reference voltage, the result of a/d conversion is 3ffh. 4. flash memory rewrite disabled. except for the analog input pin, set the pins to be measured as input ports and connect them to v ss . see figure 5.2 ?a/d accuracy measure circuit?. 5.1.4 d/a conversion characteristics notes: 1. this applies when using one d/a converter, with the d/a register for the unused d/a converter set to 00h. 2. the current consumption of the a/d converter is not included. also, the i vref of the d/a converter will flow even if the adstby bit in the adcon1 register is 0 (a/d operation stopped (standby)). table 5.6 a/d conversion characteristics (2/2) (1) v cc1 = av cc = 3.0 to 5.5 v v cc2 v ref , v ss = av ss = 0 v at t opr = -20 c to 85 c/-40 c to 85 c unless otherwise specified. symbol parameter measuring condition standard unit min. typ. max. ad a/d operating clock frequency an0 to an7 input, anex0 to anex1 input 4.0 v v cc1 5.5 v 2 25 mhz 3.2 v v cc1 4.0 v 2 16 mhz 3.0 v v cc1 3.2 v 2 10 mhz an0_0 to an0_7 input, an2_0 to an2_7 input 4.0 v v cc2 5.5 v 2 25 mhz 3.2 v v cc2 4.0 v 2 16 mhz 3.0 v v cc2 3.2 v 2 10 mhz - tolerance level impedance 3 k d nl differential non-linearity error (4) 1 lsb - offset error (4) 3 lsb - gain error (4) 3 lsb t conv 10-bit conversion time v cc1 = 5 v, ad = 25 mhz 1.60 s t samp sampling time 0.60 s v ref reference voltage 3.0 v cc1 v v ia analog input voltage (2), (3) 0v ref v table 5.7 d/a conver sion characteristics v cc1 = av cc = v ref = 3.0 to 5.5 v, v ss = av ss = 0 v at t opr = -20 c to 85 c/-40 c to 85 c unless otherwise specified. symbol parameter measuring condition standard unit min. typ. max. -r e s o l u t i o n 8bits - absolute accuracy 2.5 lsb t su setup time 3 s r o output resistance 568.2k i vref reference power supply input current see notes 1 and 2 1.5 ma
r01ds0031ej0210 rev.2.10 page 57 of 111 jul 31, 2012 m16c/65 group 5. electrical characteristics 5.1.5 flash memory el ectrical characteristics notes: 1. set the pm17 bit in the pm1 register to 1 (one wait). 2. when the frequency is over this value, set the fmr17 bit in the fmr1 register to 0 (one wait) or the pm17 bit in the pm1 register to 1 (one wait) 3. set the pm17 bit in the pm1 register to 1 (one wait). w hen using 125 khz on-chip oscillator clock or sub clock as the cpu clock source, a wait is not necessary. notes: 1. definition of prog ram and erase cycles: the program and erase cycles refer to the number of per-block erasures. if the program and erase cycles are n (n = 1,000), each block can be erased n times. for example, if a block is erased after writing 2 word data 16,384 times, each to a different address, this counts as one program and erase cycles. data cannot be written to the same address more than once without erasing the block (rewrite prohibited). 2. cycles to guarantee all electrical characteristics after program and erase. (1 to min. value can be guaranteed). 3. in a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential addresses in turn so that as much of the block as possible is used up before performing an erase operation. it is advisable to retain data on the erasure cycles of each block and limit the number of erase operations to a certain number. 4. if an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase command at least three times until the erase error does not occur. 5. customers desiring program/erase failure rate information should contact a renesas electronics sales office. 6. the data hold time includes time that the power supply is off or the clock is not supplied. table 5.8 cpu clock when operating flash memory (f (bclk) ) v cc1 = 2.7 to 5.5 v, t opr = -20 c to 85 c/-40 c to 85 c unless otherwise specified. symbol parameter conditions standard unit min. typ. max. -c p u r e w r i t e m o d e 10 (1) mhz f(slow_r) slow read mode 5 (3) mhz - low current consumption read mode fc(32.768) 35 khz - data flash read 2.7 v v cc1 3.0 v 16 (2) mhz 3.0 v < v cc1 5.5 v 20 (2) mhz table 5.9 flash memory (program ro m 1, 2) electrical characteristics v cc1 = 2.7 to 5.5 v at t opr = 0 c to 60 c (option: -40 c to 85 c), unless otherwise specified. symbol parameter conditions standard unit min. typ. max. - program and erase cycles (1), (3), (4) v cc1 = 3.3 v, t opr = 25 c 1,000 (2) times - 2 word program time v cc1 = 3.3 v, t opr = 25 c 150 4000 s - lock bit program time v cc1 = 3.3 v, t opr = 25 c 70 3000 s - block erase time v cc1 = 3.3 v, t opr = 25 c 0.2 3.0 s - program, erase voltage 2.7 5.5 v - read voltage t opr = -20 c to 85 c/-40 c to 85 c 2.7 5.5 v - program, erase temperature 0 60 c t ps flash memory circuit stabilization wait time 50 s - data hold time (6) ambient temperature = 55 c20 year
r01ds0031ej0210 rev.2.10 page 58 of 111 jul 31, 2012 m16c/65 group 5. electrical characteristics notes: 1. definition of pr ogram and erase cycles the program and erase cycles refer to the number of per-block erasures. if the program and erase cycles are n (n = 10, 000), each block can be erased n times. for example, if a 4 kb block is erased after writing 2 wo rd data 1,024 times, each to a different address, this counts as one program and erase cycles. data cannot be written to the same address more than once without erasing the block (rewrite prohibited). 2. cycles to guarantee all electrical characteristics after program and erase. (1 to min. value can be guaranteed). 3. in a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential addresses in turn so that as much of the block as possible is used up before performing an erase operation. for example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 256 groups before erasing them all in one operation. in addition, averaging the erasure cycles between blocks a and b ca n further reduce the actual erasure cycles. it is also ad visable to retain data on the erasure cycles of each block and limit the number of eras e operations to a certain number. 4. if an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase command at least three times until the erase error does not occur. 5. customers desiring program/erase failure rate information should contact a renesas electronics sales office. 6. the data hold time includes time that the power supply is off or the clock is not supplied. table 5.10 flash memory (data flash) electrical characteristics v cc1 = 2.7 to 5.5 v at t opr = -20 to 85 c/-40 to 85 c, unless otherwise specified. symbol parameter conditions standard unit min. typ. max. - program and erase cycles (1), (3), (4) v cc1 = 3.3 v, t opr = 25 c 10,000 (2) times - 2 word program time v cc1 = 3.3 v, t opr = 25 c 300 4000 s - lock bit program time v cc1 = 3.3 v, t opr = 25 c 140 3000 s - block erase time v cc1 = 3.3 v, t opr = 25 c 0.2 3.0 s - program, erase voltage 2.7 5.5 v - read voltage 2.7 5.5 v - program, erase temperature ? 20/ ? 40 85 c t ps flash memory circuit stabilization wait time 50 s - data hold time (6) ambient temperature = 55 c 20 year
r01ds0031ej0210 rev.2.10 page 59 of 111 jul 31, 2012 m16c/65 group 5. electrical characteristics 5.1.6 voltage detector and power supp ly circuit electrical characteristics notes: 1. select the voltage detection level with the vdsel1 bit in the ofs1 address. 2. necessary time until the voltage detector operates when setting to 1 again after setting the vc25 bit in the vcr2 register to 0. 3. time from when passing the v det0 until when a voltage monitor 0 reset is generated. notes: 1. select the voltage detection level with bits vd1s0 to vd1s3 in the vd1ls register. 2. necessary time until the voltage detector operates when setting to 1 again after setting the vc26 bit in the vcr2 register to 0. 3. time from when passing the v det1 until when a voltage monitor 1 reset is generated. table 5.11 voltage detector 0 electrical characteristics the measurement condition is v cc1 = 2.7 to 5.5 v, t opr = -20 c to 85 c/-40 c to 85 c, unless otherwise specified. symbol parameter condition standard unit min. typ. max. v det0 voltage detection level vdet0_0 (1) when v cc1 is falling. 1.60 1.90 2.20 v voltage detection level vdet0_2 (1) when v cc1 is falling. 2.55 2.85 3.15 v - voltage detector 0 response time (3) when v cc1 falls from 5 v to (vdet0_0 - 0.1) v 200 s - voltage detector self power consumption vc25 = 1, v cc1 = 5.0 v 1.8 a t d(e-a) waiting time until voltage detector operation starts (2) 100 s table 5.12 voltage detector 1 electrical characteristics the measurement condition is v cc1 = 2.7 to 5.5 v, t opr = -20 c to 85 c/-40 c to 85 c, unless otherwise specified. symbol parameter condition standard unit min. typ. max. v det1 voltage detection level vdet1_6 (1) when v cc1 is falling. 2.79 3.09 3.39 v voltage detection level vdet1_b (1) when v cc1 is falling. 3.54 3.84 4.14 v voltage detection level vdet1_f (1) when v cc1 is falling. 3.94 4.44 4.94 v - hysteresis width when v cc1 of voltage detector 1 is rising 0.15 v - voltage detector 1 response time (3) when v cc1 falls from 5 v to (vdet1_0 - 0.1) v 200 s - voltage detector self power consumption vc26 = 1, v cc1 = 5.0 v 1.8 a t d(e-a) waiting time until voltage detector operation starts (2) 100 s
r01ds0031ej0210 rev.2.10 page 60 of 111 jul 31, 2012 m16c/65 group 5. electrical characteristics notes: 1. necessary time until the voltage detector operates after setting to 1 again after setting the vc27 bit in the vcr2 register to 0. 2. time from when passing the v det2 until when a voltage monitor 2 reset is generated. note: 1. to use the power-on reset function, enable voltage monitor 0 reset by setting the lvdas bit in the ofs1 address to 0. also, set the vdsel1 bit to 0 (vdet0_2). figure 5.3 power-on reset circui t electrical characteristics table 5.13 voltage detector 2 electrical characteristics the measurement condition is v cc1 = 2.7 to 5.5 v, t opr = -20 c to 85 c/-40 c to 85 c, unless otherwise specified. symbol parameter condition standard unit min. typ. max. v det2 voltage detection level vdet2_0 when v cc1 is falling 3.50 4.00 4.50 v - hysteresis width at the rising of v cc1 in voltage detector 2 0.15 v - voltage detector 2 response time (2) when v cc1 falls from 5 v to (vdet2_0 - 0.1) v 200 s - voltage detector self power consumption vc27 = 1, v cc1 = 5.0 v 1.8 a t d(e-a) waiting time until voltage detector operation starts (1) 100 s table 5.14 power-on reset circuit the measurement condition is v cc1 = 2.0 to 5.5 v, t opr = -20 c to 85 c/ -40 c to 85 c, unless otherwise specified. symbol parameter condition standard unit min. typ. max. v por1 voltage at which power-on reset enabled (1) 0.1 v t rth external power v cc1 rise gradient 2.0 50000 mv/ms t w(por) time necessary to enable power-on reset 300 ms vpor1 internal reset signal voltage detection 0 circuit response time 1 f oco-s 32 v cc1 v (1) det0 t rth t w(por) t rth v (1) det0 1 f oco-s 32 note: 1. v det0 indicates the voltage detection level of the voltage detection 0 circuit.
r01ds0031ej0210 rev.2.10 page 61 of 111 jul 31, 2012 m16c/65 group 5. electrical characteristics note: 1. waiting time until the internal power supply generator stabilizes when power is on. figure 5.4 power supply circuit timing diagram table 5.15 power supply circuit timing characteristics the measurement condition is v cc1 = 2.7 to 5.5 v and t opr = 25 c, unless otherw ise specified. symbol parameter condition standard unit min. typ. max. t d(p-r) internal power supply stabilit y time when power is on (1) 5ms t d(r-s) stop release time 150 s t d(w-s) low power mode wait mode release time 150 s cpu clock t d(p-r) internal power supply stability time when power is on interrupt for (a) stop mode release or (b) wait mode release cpu clock (a) (b) t d(r-s) stop release time t d(w-s) low power mode wait mode release time vc25, vc26, vc27 t d(e-a) voltage detector operation start time stop operate recommended operation voltage voltage detector v cc1 t d(p-r) t d(r-s) t d(w-s) t d(e-a)
r01ds0031ej0210 rev.2.10 page 62 of 111 jul 31, 2012 m16c/65 group 5. electrical characteristics 5.1.7 oscillator elect rical characteristics table 5.16 40 mhz on-chip oscillator electrical charac teristics (1/2) r5f36506nfa, r5f36506nfb, r5f36506dfa, r5f36506dfb, r5f3651enfc, r5f3650enfa, r5f3650enfb, r5f3651edfc, r5f3650edfa, r5f3650edfb, r5f3651knfc, r5f3650knfa, r5f3650knfb, r5f3651kdfc, r5f3650kdfb, r5f3650kdfa, r5f3651mnfc, r5f3650mnfa, r5f3650mnfb, r5f3651mdfc, r5f3650mdfa, r5f3650mdfb, r5f3651nnfc, r5f3650nnfa, r5f3650nnfb, r5f3651ndfc, r5f3650ndfa, r5f3650ndfb v cc1 = 2.7 to 5.5 v, t opr = -20 c to 85 c/-40 c to 85 c, unless otherwise specified. symbol parameter condition standard unit min. typ. max. f oco40m 40 mhz on-chip oscillator frequency average frequency in a 10 ms period 36 40 44 mhz tsu(f oco40m ) wait time until 40 mhz on-chip oscillator stabilizes 2ms table 5.17 40 mhz on-chip oscillator electrical charac teristics (2/2) r5f3651rnfc, r5f3650rnfa, r5f3650rnfb, r5f3651 rdfc, r5f3650rdfa, r5f3650rdfb, r5f3651tnfc, r5f3650tnfa, r5f3650tnfb, r5f3651tdfc, r5f3650tdfa, r5f3650tdfb v cc1 = 2.7 to 5.5 v, t opr = -20 c to 85 c/-40 c to 85 c, unless otherwise specified. symbol parameter condition standard unit min. typ. max. f oco40m 40 mhz on-chip oscillator frequency average frequency in a 10 ms period 2.7 v v cc1 < 5.5 v, t opr = 25 c 36 40 44 mhz average frequency in a 10 ms period 1 40 60 mhz tsu(f oco40m ) wait time until 40 mhz on-chip oscillator stabilizes 2ms table 5.18 125 khz on-c hip oscillator electrical characteristics v cc1 = 2.7 to 5.5 v, t opr = ? 20 c to 85 c/ ? 40 c to 85 c, unless otherwise specified. symbol parameter condition standard unit min. typ. max. f oco-s 125 khz on-chip oscillator frequency average frequency in a 10 ms period 100 125 150 khz tsu(f oco-s ) wait time until 125 khz on-chip oscillator stabilizes 20 s
r01ds0031ej0210 rev.2.10 page 63 of 111 jul 31, 2012 m16c/65 group 5. electrical characteristics 5.2 electrical characteristics (v cc1 = v cc2 = 5 v) 5.2.1 electrical characteristics v cc1 = v cc2 = 5 v note: 1. when v cc1 v cc2 , refer to 5 v or 3 v standard depending on the voltage. table 5.19 electrical characteristics (1) (1) v cc1 = v cc2 = 4.2 to 5.5 v, v ss = 0 v at t opr = ? 20 c to 85 c/ ? 40 c to 85 c, f (bclk) = 32 mhz unless otherwise specified. symbol parameter measuring condition standard unit min. typ. max. v oh high output voltage p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_7, p14_0, p14_1 i oh = ? 5 ma v cc1 ? 2.0 v cc1 v p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p12_0 to p12_7, p13_0 to p13_7 i oh = ? 5 ma v cc2 ? 2.0 v cc2 v oh high output voltage p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_7, p14_0, p14_1 i oh = ? 200 av cc1 ? 0.3 v cc1 v p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p12_0 to p12_7, p13_0 to p13_7 i oh = ? 200 a v cc2 ? 0.3 v cc2 v oh high output voltage xout high power i oh = ? 1 ma v cc1 ? 2.0 v cc1 v low power i oh = ? 0.5 ma v cc1 ? 2.0 v cc1 high output voltage xcout high power with no load applied 2.6 v low power with no load applied 2.2 v ol low output voltage p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_7, p14_0, p14_1 i ol = 5 ma 2.0 v p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p12_0 to p12_7, p13_0 to p13_7 i ol = 5 ma 2.0 v ol low output voltage p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_7, p14_0, p14_1 i ol = 200 a0 . 4 5 v p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p12_0 to p12_7, p13_0 to p13_7 i ol = 200 a 0.45 v ol low output voltage xout high power i ol = 1 ma 2.0 v low power i ol = 0.5 ma 2.0 low output voltage xcout high power with no load applied 0v low power with no load applied 0
r01ds0031ej0210 rev.2.10 page 64 of 111 jul 31, 2012 m16c/65 group 5. electrical characteristics v cc1 = v cc2 = 5 v note: 1. when v cc1 v cc2 , refer to 5 v or 3 v standard depending on the voltage. table 5.20 electrical characteristics (2) (1) v cc1 = v cc2 = 4.2 to 5.5 v, v ss = 0 v at t opr = ? 20 c to 85 c/ ? 40 c to 85 c, f (bclk) = 32 mhz unless otherwise specified. symbol parameter measuring condition standard unit min. typ. max. v t+ - v t- hysteresis hold , rdy , ta0in to ta4in, tb0in to tb5in, int0 to int7 , nmi , adtrg , cts0 to cts2 , cts5 to cts7, scl0 to scl2, scl5 to scl7, sda0 to sda2, sda5 to sda7, clk0 to clk7, ta0out to ta4out, ki0 to ki3 , rxd0 to rxd2, rxd5 to rxd7, sin3, sin4, sd , pmc0, pmc1, sclmm, sdamm, cec , zp, idu, idv, idw 0.5 2.0 v v t+ - v t- hysteresis reset 0.5 2.5 v i ih high input current p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_7, p12_0 to p12_7, p13_0 to p13_7, p14_0, p14_1 xin, reset , cnvss, byte v i = 5 v 5.0 a i il low input current p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_7, p12_0 to p12_7, p13_0 to p13_7, p14_0, p14_1 xin, reset , cnvss, byte v i = 0 v ? 5.0 a r pullup pull-up resistance p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_7, p12_0 to p12_7, p13_0 to p13_7, p14_0, p14_1 v i = 0 v 30 50 100 k r fxin feedback resistance xin 1.5 m v ram ram retention voltage in stop mode 1.8 v
r01ds0031ej0210 rev.2.10 page 65 of 111 jul 31, 2012 m16c/65 group 5. electrical characteristics v cc1 = v cc2 = 5 v note: 1. this indicates the memory in which the program to be executed exists. table 5.21 electrical characteristics (3) r5f36506nfa, r5f36506nfb, r5f36506dfa, r5f36506dfb, r5f3650enfa, r5f3650enfb, r5f3650edfa, r5f3650edfb v cc1 = v cc2 = 4.2 to 5.5 v, v ss = 0 v at t opr = ? 20 c to 85 c/ ? 40 c to 85 c, f (bclk) = 32 mhz unless otherwise specified. symbol parameter measuring condition standard unit min. typ. max. r fxcin feedback resistance xcin 8m i cc power supply current in single-chip, mode, the output pin are open and other pins are v ss high-speed mode f (bclk) = 32 mhz xin = 4 mhz (square wave), pll multiplied by 8 125 khz on-chip oscillator stopped 24.0 ma f (bclk) =32 mhz, a/d conversion xin = 4 mhz (square wave), pll multiplied by 8 125 khz on-chip oscillator stopped 24.7 ma f (bclk) = 20 mhz xin = 20 mhz (square wave) 125 khz on-chip oscillator stopped 16.0 ma 40 mhz on-chip oscillator mode main clock stopped 40 mhz on-chip oscillator on, divide-by-4 (f (bclk) = 10 mhz) 125 khz on-chip oscillator stopped 17.0 ma 125 khz on-chip oscillator mode main clock stopped 40 mhz on-chip oscillator stopped, 125 khz on-chip oscillator on, no division fmr22 = 1 (slow read mode) 500.0 a low-power mode f (bclk) = 32 khz in low-power mode fmr22 = fmr23 = 1 on flash memory (1) 160.0 a f (bclk) = 32 khz in low-power mode on ram (1) 45.0 a wait mode main clock stopped 40 mhz on-chip oscillator stopped 125 khz on-chip oscillator on peripheral clock operating t opr = 25 c 20.0 a f (bclk) = 32 khz (oscillation capacity high) 40 mhz on-chip oscillator stopped 125 khz on-chip oscillator stopped peripheral clock operating t opr = 25 c 11.0 a f (bclk) = 32 khz (oscillation capacity low) 40 mhz on-chip oscillator stopped 125 khz on-chip oscillator stopped peripheral clock operating t opr = 25 c 6.0 a stop mode main clock stopped 40 mhz on-chip oscillator stopped 125 khz on-chip oscillator stopped peripheral clock stopped t opr = 25 c 1.7 a during flash memory program f (bclk) = 10 mhz, pm17 = 1 (one wait) v cc1 = 5.0 v 20.0 ma during flash memory erase f (bclk) = 10 mhz, pm17 = 1 (one wait) v cc1 = 5.0 v 30.0 ma
r01ds0031ej0210 rev.2.10 page 66 of 111 jul 31, 2012 m16c/65 group 5. electrical characteristics v cc1 = v cc2 = 5 v note: 1. this indicates the memory in which the program to be executed exists. table 5.22 electrical characteristics (4) r5f3651enfc, r5f3651edfc, r5f3651knfc, r5f3650knfa, r5f3650knfb, r5f3651kdfc, r5f3650kdfb, r5f3650kdfa, r5f3651mnfc, r5f3650mnfa, r5f3650mnfb, r5f3651mdfc, r5f3650mdfa, r5f3650mdfb, r5f3651nnfc, r5f3650nnfa, r5f3650nnfb, r5f3651ndfc, r5f3650ndfa, r5f3650ndfb v cc1 = v cc2 = 4.2 to 5.5 v, v ss = 0 v at t opr = ?20 c to 85 c/ ?40 c to 85 c, f (bclk) = 32 mhz unless otherwise specified. symbol parameter measuring condition standard unit min. typ. max. r fxcin feedback resistance xcin 8m i cc power supply current in single-chip, mode, the output pin are open and other pins are v ss high-speed mode f (bclk) = 32 mhz xin = 4 mhz (square wave), pll multiplied by 8 125 khz on-chip oscillator stopped 26.0 ma f (bclk) = 32 mhz, a/d conversion xin = 4 mhz (square wave), pll multiplied by 8 125 khz on-chip oscillator stopped 27.0 ma f (bclk) = 20 mhz xin = 20 mhz (square wave) 125 khz on-chip oscillator stopped 17.0 ma 40 mhz on-chip oscillator mode main clock stopped 40 mhz on-chip oscillator on, divide-by-4 (f(bclk) = 10 mhz) 125 khz on-chip oscillator stopped 18.0 ma 125 khz on-chip oscillator mode main clock stopped 40 mhz on-chip oscillator stopped 125 khz on-chip oscillator on, no division fmr22 = 1 (slow read mode) 550.0 a low-power mode f (bclk) = 32 khz in low-power mode fmr22 = fmr23 = 1 on flash memory (1) 170.0 a f (bclk) = 32 khz in low-power mode on ram (1) 45.0 a wait mode main clock stopped 40 mhz on-chip oscillator stopped 125 khz on-chip oscillator on peripheral clock operating t opr = 25 c 20.5 a f (bclk) = 32 khz (oscillation capacity high) 40 mhz on-chip oscillator stopped 125 khz on-chip oscillator stopped peripheral clock operating t opr = 25 c 11.0 a f (bclk) = 32 khz (oscillation capacity low) 40 mhz on-chip oscillator stopped 125 khz on-chip oscillator stopped peripheral clock operating t opr = 25 c 6.0 a stop mode main clock stopped 40 mhz on-chip oscillator stopped 125 khz on-chip oscillator stopped peripheral clock stopped t opr = 25 c 1.7 a during flash memory program f (bclk) = 10 mhz, pm17 = 1 (one wait) v cc1 = 5.0 v 20.0 ma during flash memory erase f (bclk) = 10 mhz, pm17 = 1 (one wait) v cc1 = 5.0 v 30.0 ma
r01ds0031ej0210 rev.2.10 page 67 of 111 jul 31, 2012 m16c/65 group 5. electrical characteristics v cc1 = v cc2 = 5 v note: 1. this indicates the memory in which the program to be executed exists. table 5.23 electrical characteristics (5) r5f3651rnfc, r5f3650rnfa, r5f3650rnfb, r5f3651 rdfc, r5f3650rdfa, r5f3650rdfb, r5f3651tnfc, r5f3650tnfa, r5f3650tnfb, r5f3651tdfc, r5f3650tdfa, r5f3650tdfb v cc1 = v cc2 = 4.2 to 5.5 v, v ss = 0 v at t opr = ? 20 to 85 c/ ? 40 to 85 c, f (bclk) = 32 mhz unless otherwise specified. symbol parameter measuring condition standard unit min. typ. max. r fxcin feedback resistance xcin 15 m i cc power supply current in single-chip, mode, the output pin are open and other pins are v ss high-speed mode f (bclk) = 32 mhz xin = 4 mhz (square wave), pll multiplied by 8 125 khz on-chip oscillator stopped 32.0 ma f (bclk) = 32 mhz, a/d conversion xin = 4 mhz (square wave), pll multiplied by 8 125 khz on-chip oscillator stopped 32.7 ma f (bclk) = 20 mhz xin = 20 mhz (square wave) 125 khz on-chip oscillator stopped 21.0 ma 40 mhz on-chip oscillator mode main clock stopped 40 mhz on-chip oscillator on, divide-by-4 (f(bclk) = 10 mhz) 125 khz on-chip oscillator stopped 23.0 ma 125 khz on-chip oscillator mode main clock stopped 40 mhz on-chip oscillator stopped 125 khz on-chip oscillator on, no division fmr22 = 1 (slow read mode) 750.0 a low-power mode f (bclk) = 32 khz in low-power mode fmr22 = fmr23 = 1 on flash memory (1) 250.0 a f (bclk) = 32 khz in low-power mode on ram (1) 45.0 a wait mode main clock stopped 40 mhz on-chip oscillator stopped 125 khz on-chip oscillator on peripheral clock operating t opr = 25 c 21.0 a f (bclk) = 32 khz (oscillation capacity high) 40 mhz on-chip oscillator stopped 125 khz on-chip oscillator stopped peripheral clock operating t opr = 25 c 11.0 a f (bclk) = 32 khz (oscillation capacity low) 40 mhz on-chip oscillator stopped 125 khz on-chip oscillator stopped peripheral clock operating t opr = 25 c 6.0 a stop mode main clock stopped 40 mhz on-chip oscillator stopped 125 khz on-chip oscillator stopped peripheral clock stopped t opr = 25 c 1.7 a during flash memory program f (bclk) = 10 mhz, pm17 = 1 (one wait) v cc1 = 5.0 v 20.0 ma during flash memory erase f (bclk) = 10 mhz, pm17 = 1 (one wait) v cc1 = 5.0 v 30.0 ma
r01ds0031ej0210 rev.2.10 page 68 of 111 jul 31, 2012 m16c/65 group 5. electrical characteristics v cc1 = v cc2 = 5 v 5.2.2 timing requirements (per ipheral functions and others) (v cc1 = v cc2 = 5 v, v ss = 0 v, at t opr = -20 c to 85 c/-40 c to 85 c unless otherwise specified) 5.2.2.1 reset input ( reset input) figure 5.5 reset input ( reset input) 5.2.2.2 external clock input note: 1. the condition is v cc1 = v cc2 = 3.0 to 5.0 v. figure 5.6 external clock input (xin input) table 5.24 reset input ( reset input) symbol parameter standard unit min. max. t w(rstl) reset input low pulse width 10 s table 5.25 external clock input (xin input) (1) symbol parameter standard unit min. max. t c external clock input cycle time 50 ns t w(h) external clock inpu t high pulse width 20 ns t w(l) external clock input low pulse width 20 ns t r external clock rise time 9n s t f external clock fall time 9n s reset input t w(rtsl) xin input t w(h) t r t f t w(l) t c
r01ds0031ej0210 rev.2.10 page 69 of 111 jul 31, 2012 m16c/65 group 5. electrical characteristics v cc1 = v cc2 = 5 v timing requirements (v cc1 = v cc2 = 5 v, v ss = 0 v, at t opr = -20 c to 85 c/-40 c to 85 c unless otherwise specified) 5.2.2.3 timer a input figure 5.7 timer a input table 5.26 timer a input (counter input in event counter mode) symbol parameter standard unit min. max. t c(ta) taiin input cycle time 100 ns t w(tah) taiin input high pulse width 40 ns t w(tal) taiin input low pulse width 40 ns table 5.27 timer a input (gating input in timer mode) symbol parameter standard unit min. max. t c(ta) taiin input cycle time 400 ns t w(tah) taiin input high pulse width 200 ns t w(tal) taiin input low pulse width 200 ns table 5.28 timer a input (external trigger input in one-shot timer mode) symbol parameter standard unit min. max. t c(ta) taiin input cycle time 200 ns t w(tah) taiin input high pulse width 100 ns t w(tal) taiin input low pulse width 100 ns table 5.29 timer a input (external trigger input in pulse width modulation mode and programmable output mode) symbol parameter standard unit min. max. t w(tah) taiin input high pulse width 100 ns t w(tal) taiin input low pulse width 100 ns taiin input taiout input t w(tah) t c(ta) t w(tal) t c(up) t w(uph) t w(upl)
r01ds0031ej0210 rev.2.10 page 70 of 111 jul 31, 2012 m16c/65 group 5. electrical characteristics v cc1 = v cc2 = 5 v timing requirements (v cc1 = v cc2 = 5 v, v ss = 0 v, at t opr = -20 c to 85 c/-40 c to 85 c unless otherwise specified) figure 5.8 timer a input (two-phase pulse input in event counter mode) table 5.30 timer a input (two-phase pulse input in event counter mode) symbol parameter standard unit min. max. t c(ta) taiin input cycle time 800 ns t su(tain-taout) taiout input setup time 200 ns t su(taout-tain) taiin input setup time 200 ns taiin input two-phase pulse input in event counter mode taiout input t c(ta) t su(tain-taout) t su(tain-taout) t su(taout-tain) t su(taout-tain)
r01ds0031ej0210 rev.2.10 page 71 of 111 jul 31, 2012 m16c/65 group 5. electrical characteristics v cc1 = v cc2 = 5 v timing requirements (v cc1 = v cc2 = 5 v, v ss = 0 v, at t opr = -20 c to 85 c/-40 c to 85 c unless otherwise specified) 5.2.2.4 timer b input figure 5.9 timer b input table 5.31 timer b input (counter input in event counter mode) symbol parameter standard unit min. max. t c(tb) tbiin input cycle time (counted on one edge) 100 ns t w(tbh) tbiin input high pulse width (counted on one edge) 40 ns t w(tbl) tbiin input low pulse width (counted on one edge) 40 ns t c(tb) tbiin input cycle time (counted on both edges) 200 ns t w(tbh) tbiin input high pulse width (counted on both edges) 80 ns t w(tbl) tbiin input low pulse width (counted on both edges) 80 ns table 5.32 timer b input (pul se period measurement mode) symbol parameter standard unit min. max. t c(tb) tbiin input cycle time 400 ns t w(tbh) tbiin input high pulse width 200 ns t w(tbl) tbiin input low pulse width 200 ns table 5.33 timer b input (pulse width measurement mode) symbol parameter standard unit min. max. t c(tb) tbiin input cycle time 400 ns t w(tbh) tbiin input high pulse width 200 ns t w(tbl) tbiin input low pulse width 200 ns tbiin input t c(tb) t w(tbh) t w(tbl)
r01ds0031ej0210 rev.2.10 page 72 of 111 jul 31, 2012 m16c/65 group 5. electrical characteristics v cc1 = v cc2 = 5 v timing requirements (v cc1 = v cc2 = 5 v, v ss = 0 v, at t opr = -20 c to 85 c/-40 c to 85 c unless otherwise specified) 5.2.2.5 serial interface figure 5.10 serial interface 5.2.2.6 external interrupt inti input figure 5.11 external interrupt inti input table 5.34 serial interface symbol parameter standard unit min. max. t c(ck) clki input cycle time 200 ns t w(ckh) clki input high pulse width 100 ns t w(ckl) clki input low pulse width 100 ns t d(c-q) txdi output delay time 80 ns t h(c-q) txdi hold time 0n s t su(d-c) rxdi input setup time 70 ns t h(c-d) rxdi input hold time 90 ns table 5.35 external interrupt inti input symbol parameter standard unit min. max. t w(inh) inti input high pulse width 250 ns t w(inl) inti input low pulse width 250 ns clki txdi rxdi t c(ck) t w(ckh) t w(ckl) t h(c-q) t d(c-q) t su(d-c) t h(c-d) inti input t w(inl) t w(inh)
r01ds0031ej0210 rev.2.10 page 73 of 111 jul 31, 2012 m16c/65 group 5. electrical characteristics v cc1 = v cc2 = 5 v timing requirements (v cc1 = v cc2 = 5 v, v ss = 0 v, at t opr = -20 c to 85 c/-40 c to 85 c unless otherwise specified) 5.2.2.7 multi-master i 2 c-bus figure 5.12 multi-master i 2 c-bus table 5.36 multi-master i 2 c-bus symbol parameter standard clock mode fast-mode unit min. max. min. max. t buf bus free time 4.7 1.3 s t hd;sta hold time in start condition 4.0 0.6 s t low hold time in scl clock 0 status 4.7 1.3 s t r scl, sda signals? rising time 1000 20 + 0.1 cb 300 ns t hd;dat data hold time 00 0 . 9 s t high hold time in scl clock 1 status 4.0 0.6 s f f scl, sda signals? falling time 300 20 + 0.1 cb 300 ns t su;dat data setup time 250 100 ns t su;sta setup time in restart condition 4.7 0.6 s t su;sto stop condition setup time 4.0 0.6 s sda scl p ps sr t low t hd;sta t hd;dat t high t su;dat t su;sta t r t f t hd;sta t su;sto t buf
r01ds0031ej0210 rev.2.10 page 74 of 111 jul 31, 2012 m16c/65 group 5. electrical characteristics v cc1 = v cc2 = 5 v timing requirements (v cc1 = v cc2 = 5 v, v ss = 0 v, at t opr = -20 c to 85 c/-40 c to 85 c unless otherwise specified) 5.2.3 timing requirements (memory expansion mode and microprocessor mode) notes: 1. calculated according to the bclk frequency as follows: 2. calculated according to the bclk frequency as follows: n is 1 for 1 wait setting, 2 for 2 waits setting and 3 for 3 waits setting. 3. calculated according to the bclk frequency as follows: n is 2 for 2 waits setting, and 3 for 3 waits setting. 4. calculated according to the bclk frequency as follows: n is 3 for 2 + 3 , 4 for 2 + 4 , 4 for 3 + 4 , and 5 for 4 + 5 . table 5.37 memory expansion mode and microprocessor mode symbol parameter standard unit min. max. t ac1(rd-db) data input access time (for setting with no wait) (note 1) ns t ac2(rd-db) data input access time (for setting with 1 to 3 waits) (note 2) ns t ac3(rd-db) data input access time (when accessing multiplex bus area) (note 3) ns t ac4(rd-db) data input access time (for setting with 2 + 3 or more) (note 4) ns t su(db-rd) data input setup time 40 ns t su(rdy-bclk) rdy input setup time 80 ns t h(rd-db) data input hold time 0ns t h(bclk-rdy) rdy input hold time 0n s 0.5 10 9 f bclk () ns [] n 0.5 + () f bclk () ns [] n 0.5 ? () f bclk () ns [] n 10 9 f bclk () ns []
r01ds0031ej0210 rev.2.10 page 75 of 111 jul 31, 2012 m16c/65 group 5. electrical characteristics figure 5.13 timing diagram memory expansion mode and microprocessor mode ( effective in wait state setting ) rdy input rd bclk (separate bus) (multiplexed bus) rd (separate bus) (multiplexed bus) t su(rdy-bclk) t h(bclk-rdy) measuring conditions y v = v = 5 v cc1 cc2 y input timing voltage: v = 1.0 v, v = 4.0 v il ih y output timing voltage: v = 2.5 v, v = 2.5 v ol oh v = v = 5 v cc1 cc2 wr , wrl , wrh wr , wrl , wrh
r01ds0031ej0210 rev.2.10 page 76 of 111 jul 31, 2012 m16c/65 group 5. electrical characteristics v cc1 = v cc2 = 5 v 5.2.4 switching characteris tics (memory expansion mode and microprocessor mode) (v cc1 = v cc2 = 5 v, v ss = 0 v, at t opr = -20 c to 85 c/-40 c to 85 c unless otherwise specified) 5.2.4.1 in no wait state setting notes: 1. calculated according to the bclk frequency as follows: f (bclk) is 12.5 mhz or less. 2. calculated according to the bclk frequency as follows: 3. this standard value shows the timing when the output is off, and does not show hold time of data bus. hold time of data bus varies with capacitor volume and pull-up (pull-down) resistance value. hold time of data bus is expressed in t = ? cr ln(1 ? v ol /v cc2 ) by a circuit of the right figure. for example, when v ol = 0.2v cc2 , c = 30 pf, r = 1 k , hold time of output low level is t = ? 30 pf 1 k in(1 ? 0.2v cc2 /v cc2 ) = 6.7 ns. table 5.38 memory expansion mode and micropr ocessor mode (in no wait state setting) symbol parameter measuring condition standard unit min. max. t d(bclk-ad) address output delay time see figure 5.14 25 ns t h(bclk-ad) address output hold time (in relation to bclk) 0ns t h(rd-ad) address output hold time (in relation to rd) 0ns t h(wr-ad) address output hold time (in relation to wr) (note 2) ns t d(bclk-cs) chip select output delay time 25 ns t h(bclk-cs) chip select output hold time (in relation to bclk) 0n s t d(bclk-ale) ale signal output delay time 15 ns t h(bclk-ale) ale signal output hold time ?4n s t d(bclk-rd) rd signal output delay time 25 ns t h(bclk-rd) rd signal output hold time 0ns t d(bclk-wr) wr signal output delay time 25 ns t h(bclk-wr) wr signal output hold time 0ns t d(bclk-db) data output delay time (in relation to bclk) 40 ns t h(bclk-db) data output hold time (in relation to bclk) (3) 0n s t d(db-wr) data output delay time (in relation to wr) (note 1) ns t h(wr-db) data output hold time (in relation to wr) (3) (note 2) ns 0.5 10 9 () --------------------- -40 ns [] ? 0.5 10 9 () --------------------- -10 ns [] ? dbi r c
r01ds0031ej0210 rev.2.10 page 77 of 111 jul 31, 2012 m16c/65 group 5. electrical characteristics figure 5.14 ports p0 to p14 measurement circuit p6 p7 p8 p10 p9 p0 p1 p2 p3 p4 p5 30 pf p11 p12 p13 p14
r01ds0031ej0210 rev.2.10 page 78 of 111 jul 31, 2012 m16c/65 group 5. electrical characteristics figure 5.15 timing diagram bclk csi adi ale rd 25ns(max.) 0ns(min.) hi-z dbi 0ns(min.) bhe read timing memory expansion mode and microprocessor mode (in no wait state setting) 25ns(max.) 0ns(min.) bclk csi adi ale bhe 40ns(max.) 0ns(min.) dbi write timing hi-z 1 v = v = 5v cc1 cc2 15ns(max.) t h(bclk-cs) t cyc t h(bclk-ad) 0ns(min.) t d(bclk-ad) t d(bclk-ale) -4ns(min.) t h(rd-ad) 0ns(min.) t d(bclk-rd) t h(bclk-rd) 0ns(min.) t ac1(rd-db) t su(db-rd) t h(rd-db) t h(bclk-ale) 25ns(max.) t d(bclk-cs) 25ns(max.) t d(bclk-cs) 25ns(max.) 0ns(min.) t h(bclk-cs) t cyc 25ns(max.) 0ns(min.) 15ns(max.) t d(bclk-ale) -4ns(min.) t h(bclk-ale) t d(bclk-ad) t h(bclk-ad) t h(wr-ad) t d(bclk-wr) t h(bclk-wr) t d(bclk-db) t h(bclk-db) t d(db-wr) t h(wr-db) t = cyc measuring conditions y v = v = 5v cc1 cc2 y input timing voltage: v = 0.8 v, v = 2.0 v il ih y output timing voltage: v = 0.4 v, v = 2.4 v ol oh f (bclk) 40ns(min.) (0.5 t - 40)ns(min.) cyc (0.5 t - 10)ns(min.) cyc (0.5 t - 10)ns(min.) cyc (0.5 t - 45)ns(max.) cyc wr , wrl , wrh
r01ds0031ej0210 rev.2.10 page 79 of 111 jul 31, 2012 m16c/65 group 5. electrical characteristics v cc1 = v cc2 = 5 v switching characteristics (v cc1 = v cc2 = 5 v, v ss = 0 v, at t opr = -20 c to 85 c/-40 c to 85 c unless otherwise specified) 5.2.4.2 in 1 to 3 waits setting and when accessing external area notes: 1. calculated according to the bclk frequency as follows: 2. calculated according to the bclk frequency as follows: 3. this standard value shows the timing when the output is off, and does not show hold time of data bus. hold time of data bus varies with capacitor volume and pull-up (pull-down) resistance value. hold time of data bus is expressed in t = ? cr ln(1 ? v ol /v cc2 ) by a circuit of the right figure. for example, when v ol = 0.2v cc2 , c = 30 pf, r = 1 k , hold time of output low level is t = ? 30 pf 1 k in(1 ? 0.2v cc2 /v cc2 ) = 6.7 ns. table 5.39 memory expansion mode and microprocessor mode (in 1 to 3 waits setting and when accessing external area) symbol parameter measuring condition standard unit min. max. t d(bclk-ad) address output delay time see figure 5.14 25 ns t h(bclk-ad ) address output hold time (in relation to bclk) 0ns t h(rd-ad ) address output hold time (in relation to rd) 0n s t h(wr-ad) address output hold time (in relation to wr) (note 2) ns t d(bclk-cs) chip select output delay time 25 ns t h(bclk-cs) chip select output hold time (in relation to bclk) 0ns t d(bclk-ale) ale signal output delay time 15 ns t h(bclk-ale ) ale signal output hold time -4 ns t d(bclk-rd) rd signal output delay time 25 ns t h(bclk-rd) rd signal output hold time 0ns t d(bclk-wr) wr signal output delay time 25 ns t h(bclk-wr) wr signal output hold time 0ns t d(bclk-db) data output delay time (in relation to bclk) 40 ns t h(bclk-db) data output hold time (in relation to bclk) (3) 0n s t d(db-wr) data output delay time (in relation to wr) (note 1) ns t h(wr-db) data output hold time (in relation to wr) (3) (note 2) ns n 0.5 ? () f bclk () ns [] n is 1 for 1 wait setting, 2 for 2 waits setting and 3 for 3 waits setting. when n = 1, f (bclk) is 12.5 mhz or less. 0.5 10 9 f bclk () ns [] dbi r c
r01ds0031ej0210 rev.2.10 page 80 of 111 jul 31, 2012 m16c/65 group 5. electrical characteristics figure 5.16 timing diagram bclk csi adi ale rd hi-z dbi bhe read timing bclk csi adi ale bhe dbi write timing hi-z memory expansion mode and microprocessor mode (in 1 to 3 waits setting and when accessing external area) 1 v = v = 5v cc1 cc2 t d(bclk-cs) 25ns(max.) 0ns(min.) t cyc t h(bclk-ad) t d(bclk-ad) 25ns(max.) t d(bclk-ale) 15ns(max.) 0ns(min.) t h(bclk-cs) -4ns(min.) t h(bclk-ale) 0ns(min.) t h(rd-ad) t d(bclk-rd) 25ns(max.) 0ns(min.) t h(bclk-rd) {(n+0.5) t -45}ns(max.) cyc t su(db-rd) 0ns(min.) t h(rd-db) t d(bclk-cs) 25ns(max.) 0ns(min.) t h(bclk-cs) t cyc t d(bclk-ad) 25ns(max.) 0ns(min.) t h(bclk-ad) t d(bclk-ale) 15ns(max.) -4ns(min.) t h(bclk-ale) (0.5 t -10)ns(min.) cyc t h(wr-ad) t ac2(rd-db) t d(bclk-wr) 25ns(max.) 0ns(min.) t h(bclk-wr) t d(bclk-db) 40ns(max.) 0ns(min.) t h(wr-db) t d(db-wr) {(n-0.5) t -40}ns(min.) cyc (0.5 t -10)ns(min.) cyc t = cyc t h(bclk-db) n: 1 (when 1 wait) 2 (when 2 waits) 3 (when 3 waits) measuring conditions y v = v = 5v cc1 cc2 y input timing voltage: v = 0.8 v, v = 2.0 v il ih y output timing voltage: v = 0.4 v, v = 2.4 v ol oh f (bclk) 40ns(min.) wr , wrl , wrh
r01ds0031ej0210 rev.2.10 page 81 of 111 jul 31, 2012 m16c/65 group 5. electrical characteristics v cc1 = v cc2 = 5 v switching characteristics (v cc1 = v cc2 = 5 v, v ss = 0 v, at t opr = -20 c to 85 c/-40 c to 85 c unless otherwise specified) 5.2.4.3 in 2 or 3 waits setting, and when accessing external area and using multiplexed bus notes: 1. calculated according to the bclk frequency as follows: 2. calculated according to the bclk frequency as follows: n is 2 for 2-wait setting, 3 for 3-wait setting. 3. calculated according to the bclk frequency as follows: 4. calculated according to the bclk frequency as follows: 5. when using multiplex bus, set f (bclk) 12.5 mhz or less. table 5.40 memory expansion mode and microprocess or mode (in 2 or 3 waits setting, and when accessing external area and using multiplexed bus) (5) symbol parameter measuring condition standard unit min. max. t d(bclk-ad) address output delay time see figure 5.14 25 ns t h(bclk-ad) address output hold time (in relation to bclk) 0ns t h(rd-ad) address output hold time (in relation to rd) (note 1) ns t h(wr-ad) address output hold time (in relation to wr) (note 1) ns t d(bclk-cs) chip select output delay time 25 ns t h(bclk-cs) chip select output hold time (in relation to bclk) 0ns t h(rd-cs) chip select output hold time (in relation to rd) (note 1) ns t h(wr-cs) chip select output hold time (in relation to wr) (note 1) ns t d(bclk-rd) rd signal output delay time 25 ns t h(bclk-rd) rd signal output hold time 0ns t d(bclk-wr) wr signal output delay time 25 ns t h(bclk-wr) wr signal output hold time 0ns t d(bclk-db) data output delay time (in relation to bclk) 40 ns t h(bclk-db) data output hold time (in relation to bclk) 0ns t d(db-wr) data output delay time (in relation to wr) (note 2) ns t h(wr-db) data output hold time (in relation to wr) (note 1) ns t d(bclk-ale) ale signal output delay time (in relation to bclk) 15 ns t h(bclk-ale) ale signal output hold time (in relation to bclk) ? 4n s t d(ad-ale) ale signal output delay time (in relation to address) (note 3) ns t h(ad-ale) ale signal output hold time (in relation to address) (note 4) ns t d(ad-rd) rd signal output delay from the end of address 0ns t d(ad-wr) wr signal output delay from the end of address 0ns t dz(rd-ad) address output floating start time 8ns 0.5 10 9 () --------------------- -10 ns [] ? n 0.5 ? () 10 9 () ----------------------------------- -40 ns [] ? 0.5 10 9 () --------------------- -25 ns [] ? 0.5 10 9 () --------------------- -15 ns [] ?
r01ds0031ej0210 rev.2.10 page 82 of 111 jul 31, 2012 m16c/65 group 5. electrical characteristics figure 5.17 timing diagram memory expansion mode and microprocessor mode (in 2 or 3 waits setting, and when accessing external area and using multiplexed bus ) bclk csi adi ale rd bhe adi /dbi read timing bclk csi adi ale bhe adi /dbi data output write timing address address data input address address v = v = 5v cc1 cc2 t d(bclk-cs) 25ns(max.) t cyc (0.5 t -10)ns(min.) cyc t h(rd-cs) t h(bclk-cs) 0ns(min.) (0.5 t -25ns(min.) cyc t d(ad-ale) (0.5 t -15ns(min.) cyc t h(ale-ad) t dz(rd-ad) 8ns(max.) {(n-0.5) t -45}ns(max.) cyc t ac3(rd-db) t su(db-rd) t h(rd-db) 0ns(min.) 0ns(min.) t d(ad-rd) t h(bclk-ad) 0ns(min.) 15ns(max.) t d(bclk-ale) t h(bclk-ale) -4ns(min.) t d(bclk-ad) 25ns(max.) t h(rd-ad) (0.5 t -10)ns(min.) cyc 25ns(max.) t d(bclk-rd) 0ns(min.) t h(bclk-rd) t cyc t d(bclk-cs) 25ns(max.) (0.5 t -10)ns(min.) cyc t h(wr-cs) t h(bclk-cs) 0ns(min.) t d(bclk-db) 40ns(max.) t h(bclk-db) 0ns(min.) (0.5 t -25ns(min.) cyc t d(ad-ale) {(n-0.5) t -40}ns(min.) cyc t d(db-wr) (0.5 t -10)ns(min.) cyc t h(wr-db) t d(bclk-ad) 25ns(max.) t h(bclk-ad) 0ns(min.) 15ns(max.) t d(bclk-ale) t h(bclk-ale) -4ns(min.) 0ns(min.) t d(ad-wr) t h(wr-ad) (0.5 t -10)ns(min.) cyc 25ns(max.) t d(bclk-wr) 0ns(min.) t h(bclk-wr) n: 2 (when 2 waits) 3 (when 3 waits) measuring conditions y v = v = 5v cc1 cc2 y input timing voltage: v = 0.8 v, v = 2.0 v il ih y output timing voltage: v = 0.4 v, v = 2.4 v ol oh 40ns(min.) wr , wrl , wrh
r01ds0031ej0210 rev.2.10 page 83 of 111 jul 31, 2012 m16c/65 group 5. electrical characteristics v cc1 = v cc2 = 5 v switching characteristics (v cc1 = v cc2 = 5 v, v ss = 0 v, at t opr = -20 c to 85 c/-40 c to 85 c unless otherwise specified) 5.2.4.4 in wait state setting 2 + 3 , 2 + 4 , 3 + 4 , and 4 + 5 , and when accessing external area notes: 1. calculated according to the bclk frequency as follows: 2. calculated according to the bclk frequency as follows: 3. this standard value shows the timing when the output is off, and does not show hold time of data bus. hold time of data bus varies with capacitor volume and pull-up (pull-down) resistance value. hold time of data bus is expressed in t = ? cr ln(1 ? v ol /v cc2 ) by a circuit of the right figure. for example, when v ol = 0.2v cc2 , c = 30 pf, r = 1 k , hold time of output low level is t = ? 30 pf 1 k in(1 ? 0.2v cc2 /v cc2 ) = 6.7 ns. table 5.41 memory expansion mode and microprocessor mode (in wait state setting 2 + 3 , 2 + 4 , 3 + 4 , and 4 + 5 , and when accessing external area) symbol parameter measuring condition standard unit min. max. t d(bclk-ad) address output delay time see figure 5.14 25 ns t h(bclk-ad ) address output hold time (in relation to bclk) 0n s t h(rd-ad ) address output hold time (in relation to rd) 0n s t h(wr-ad) address output hold time (in relation to wr) (note 2) ns t d(bclk-cs) chip select output delay time 25 ns t h(bclk-cs) chip select output hold time (in relation to bclk) 0n s t d(bclk-ale) ale signal output delay time 15 ns t h(bclk-ale ) ale signal output hold time -4 ns t d(bclk-rd) rd signal output delay time 25 ns t h(bclk-rd) rd signal output hold time 0n s t d(bclk-wr) wr signal output delay time 25 ns t h(bclk-wr) wr signal output hold time 0n s t d(bclk-db) data output delay time (in relation to bclk) 40 ns t h(bclk-db) data output hold time (in relation to bclk) (3) 0n s t d(db-wr) data output delay time (in relation to wr) (note 1) ns t h(wr-db) data output hold time (in relation to wr) (3) (note 2) ns n 0.5 ? () f bclk () ns [] n is 3 for 2 + 3 , 4 for 2 + 4 , 4 for 3 + 4 , and 5 for 4 + 5 . 0.5 10 9 f bclk () ns [] dbi r c
r01ds0031ej0210 rev.2.10 page 84 of 111 jul 31, 2012 m16c/65 group 5. electrical characteristics figure 5.18 timing diagram read timing write timing bclk csi ale dbi adi bhe wr, wrl wrh bclk csi ale dbi adi bhe rd t cyc t d(bclk-cs) 25ns(max.) t d(bclk-ad) 25ns(max.) t d(bclk-ale) 15ns(max.) t h(bclk-ale) -4ns(min.) t d(bclk-rd) 25ns(max.) hi-z t su(db-rd) hi-z t d(bclk-cs) 25ns(max.) t d(bclk-ad) 25ns(max.) t d(bclk-ale) 15ns(max.) t d(bclk-wr) 25ns(max.) (0.5 t -10)ns(min.) cyc t ac4(rd-db) (n t -45)ns(max.) cyc v = v = 5v cc1 cc2 memory expansion mode and microprocessor mode (in wait state setting 2 + 3 , 2 + 4 , 3 + 4 , and 4 + 5 , and when accessing external area) n: 3 (when 2 + 3 ) 4 (when 2 + 4 or 3 + 4 ) 5 (when 4 + 5 ) t h(bclk-ad) 0ns(min.) t h(bclk-cs) 0ns(min.) t h(rd-ad) 0ns(min.) t h(bclk-rd) 0ns(min.) t h(rd-db) 0ns(min.) t h(bclk-cs) 0ns(min.) t h(bclk-ad) 0ns(min.) t h(bclk-ale) -4ns(min.) t h(wr-ad) t h(bclk-wr) 0ns(min.) t d(db-wr) t h(bclk-db) 0ns(min.) {(n-0.5) t -40}ns(min.) cyc t h(wr-db) (0.5 t -10)ns(min.) cyc measuring conditions y v = v = 5v cc1 cc2 y input timing voltage: v = 0.8 v, v = 2.0 v il ih y output timing voltage: v = 0.4 v, v = 2.4 v ol oh t cyc = 1 f(bclk) t cyc t d(bclk-db) 40ns(max.) 40ns(min.)
r01ds0031ej0210 rev.2.10 page 85 of 111 jul 31, 2012 m16c/65 group 5. electrical characteristics v cc1 = v cc2 = 5 v switching characteristics (v cc1 = v cc2 = 5 v, v ss = 0 v, at t opr = -20 c to 85 c/-40 c to 85 c unless otherwise specified) 5.2.4.5 in wait state setting 2 + 3 , 2 + 4 , 3 + 4 , and 4 + 5 , and when inserting 1 to 3 recovery cycl es and accessing external area notes: 1. calculated according to the bclk frequency as follows: 2. calculated according to the bclk frequency as follows: 3. this standard value shows the timi ng when the output is off, and does not show hold time of data bus. hold time of data bus varies with capacitor volume and pull-up (pull-down) resistance value. hold time of data bus is expressed in t = ? cr ln(1 ? v ol /v cc2 ) by a circuit of the right figure. for example, when v ol = 0.2v cc2 , c = 30 pf, r = 1 k , hold time of output low level is t = ? 30 pf 1 k in(1 ? 0.2v cc2 /v cc2 ) = 6.7 ns. 4. calculated according to the bclk frequency as follows: table 5.42 memory expansion and microprocessor modes (in wait state setting 2 + 3 , 2 + 4 , 3 + 4 , and 4 + 5 , and when inserting 1 to 3 recovery cycles and accessing external area) symbol parameter measuring condition standard unit min. max. t d(bclk-ad) address output delay time see figure 5.14 25 ns t h(bclk-ad ) address output hold time (in relation to bclk) 0n s t h(rd-ad ) address output hold time (in relation to rd) (note 4) ns t h(wr-ad) address output hold time (in relation to wr) (note 2) ns t d(bclk-cs) chip select output delay time 25 ns t h(bclk-cs) chip select output hold time (in relation to bclk) 0n s t d(bclk-ale) ale signal output delay time 15 ns t h(bclk-ale ) ale signal output hold time -4 ns t d(bclk-rd) rd signal output delay time 25 ns t h(bclk-rd) rd signal output hold time 0n s t d(bclk-wr) wr signal output delay time 25 ns t h(bclk-wr) wr signal output hold time 0n s t d(bclk-db) data output delay time (in relation to bclk) 40 ns t h(bclk-db) data output hold time (in relation to bclk) (3) 0n s t d(db-wr) data output delay time (in relation to wr) (note 1) ns t h(wr-db) data output hold time (in relation to wr) (3) (note 2) ns n 10 9 f bclk () ns [] n is 3 for 2 + 3 , 4 for 2 + 4 , 4 for 3 + 4 , and 5 for 4 + 5 . m 10 9 f bclk () ns [] m is 1 when 1 recovery cycle is inserted, 2 when 2 recovery cycles are inserted, and 3 when 3 recovery cycles are inserted. dbi r c m 10 9 f bclk () ns [] m is 1 when 1 recovery cycle is inserted, 2 when 2 recovery cycles are inserted, and 3 when 3 recovery cycles are inserted.
r01ds0031ej0210 rev.2.10 page 86 of 111 jul 31, 2012 m16c/65 group 5. electrical characteristics figure 5.19 timing diagram read timing write timing bclk csi ale dbi adi bhe bclk csi ale dbi adi bhe rd t cyc t d(bclk-cs) 25ns(max.) hi-z t su(db-rd) hi-z v = v = 5v cc1 cc2 memory expansion mode and microprocessor mode (in wait state setting 2 + 3 , 2 + 4 , 3 + 4 , and 4 + 5 , and when inserting 1 to 3 recovery cycles and accessing external area) n: 3 (when 2 + 3 ) 4 (when 2 + 4 or 3 + 4 ) 5 (when 4 + 5 ) t h(bclk-cs) 0ns(min.) t d(bclk-ad) 25ns(max.) t h(bclk-ad) 0ns(min.) t d(bclk-ale) 15ns(max.) t h(bclk-ale) -4ns(min.) t d(bclk-rd) 25ns(max.) t h(bclk-rd) 0ns(min.) t h(rd-db) 0ns(min.) t cyc t d(bclk-cs) 25ns(max.) t d(bclk-ad) 25ns(max.) t h(bclk-ale) -4ns(min.) t d(bclk-ale) 15ns(max.) t d(bclk-wr) 25ns(max.) t d(bclk-db) 40ns(max.) t h(bclk-cs) 0ns(min.) t h(bclk-ad) 0ns(min.) t h(wr-ad) (m t -10)ns(min.) cyc t h(bclk-wr) 0ns(min.) t h(bclk-db) 0ns(min.) t h(wr-db) (m t -10)ns(min.) cyc (n t -45)ns(max.) cyc t ac4(rd-db) (n t -40)ns(min.) cyc t d(db-wr) t cyc = 1 f(bclk) measuring conditions y v = v = 5v cc1 cc2 y input timing voltage: v = 0.8 v, v = 2.0 v il ih y output timing voltage: v = 0.4 v, v = 2.4 v ol oh m: 1 (when 1 recovery cycle inserted ) 2 (when 2 recovery cycles inserted) 3 (when 3 recovery cycles inserted) t h(rd-ad) (m t +0)ns(min.) cyc wr, wrl wrh 40ns(min.)
r01ds0031ej0210 rev.2.10 page 87 of 111 jul 31, 2012 m16c/65 group 5. electrical characteristics 5.3 electrical characteristics (v cc1 = v cc2 = 3 v) 5.3.1 electrical characteristics vcc1 = vcc2 = 3 v note: 1. when v cc1 v cc2 , refer to 5 v or 3 v standard depending on the voltage. table 5.43 electrical characteristics (1) (1) v cc1 = v cc2 = 2.7 to 3.3 v, v ss = 0 v at t opr = -20 c to 85 c/-40 c to 85 c, f (bclk) = 32 mhz unless otherwise specified. symbol parameter measuring condition standard unit min. typ. max. v oh high output voltage p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_7, p14_0, p14_1 i oh = ? 1 ma v cc1 ? 0.5 v cc1 v p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p12_0 to p12_7, p13_0 to p13_7 i oh = ? 1 ma v cc2 ? 0.5 v cc2 v oh high output voltage xout high power i oh = ? 0.1 ma v cc1 ? 0.5 v cc1 v low power i oh = ? 50 av cc1 ? 0.5 v cc1 high output voltage xcout high power with no load applied 2.6 v low power with no load applied 2.2 v ol low output voltage p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_7, p14_0, p14_1 i ol = 1 ma 0.5 v p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p12_0 to p12_7, p13_0 to p13_7 i ol = 1 ma 0.5 cec i ol = 1 ma 0 0.5 v v ol low output voltage xout high power i ol = 0.1 ma 0.5 v low power i ol = 50 a0 . 5 low output voltage xcout high power with no load applied 0 v low power with no load applied 0 v t+ -v t- hysteresis hold , rdy , ta0in to ta4in, tb0in to tb5in, int0 to int7 , nmi , adtrg , cts0 to cts2 , cts5 to cts7 , scl0 to scl2, scl5 to scl7, sda0 to sda2, sda5 to sda7, clk0 to clk7, ta0out to ta4out, ki0 to ki3 , rxd0 to rxd2, rxd5 to rxd7, sin3, sin4, sd , pmc0, pmc1, sclmm, sdamm, zp, idu, idv, idw 0.2 1.0 v cec 0.2 0.5 1.0 v reset 0.2 1.8 v i ih high input current p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_7, p12_0 to p12_7, p13_0 to p13_7, p14_0, p14_1 xin, reset , cnvss, byte v i = 3 v 4.0 a ? leakage current in powered-off state cec v cc1 = 0 v 1.8 a i il low input current p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_7, p12_0 to p12_7, p13_0 to p13_7, p14_0, p14_1 xin, reset , cnvss, byte v i = 0 v ? 4.0 a r pullup pull-up resistance p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_7, p12_0 to p12_7, p13_0 to p13_7, p14_0, p14_1 v i = 0 v 50 80 150 k r fxin feedback resistance xin 3.0 m v ram ram retention voltage in stop mode 1.8 v
r01ds0031ej0210 rev.2.10 page 88 of 111 jul 31, 2012 m16c/65 group 5. electrical characteristics v cc1 = v cc2 = 3 v note: 1. this indicates the memory in which the program to be executed exists. table 5.44 electrical characteristics (2) r5f36506nfa, r5f36506nfb, r5f36506dfa, r5f36506dfb, r5f3650enfa, r5f3650enfb, r5f3650edfa, r5f3650edfb v cc1 = v cc2 = 2.7 to 3.3 v, v ss = 0 v at t opr = ? 20 c to 85 c/ ? 40 c to 85 c, f (bclk) = 32 mhz unless otherwise specified. symbol parameter measuring condition standard unit min. typ. max. r fxcin feedback resistance xcin 16 m i cc power supply current in single-chip, mode, the output pin are open and other pins are v ss high-speed mode f (bclk) = 32 mhz xin = 4 mhz (square wave), pll multiplied by 8 125 khz on-chip oscillator stopped 24.0 ma f (bclk) = 32 mhz, a/d conversion xin = 4 mhz (square wave), pll multiplied by 8 125 khz on-chip oscillator stopped 24.7 ma f (bclk) = 20 mhz xin = 20 mhz (square wave) 125 khz on-chip oscillator stopped 16.0 ma 40 mhz on-chip oscillator mode main clock stopped 40 mhz on-chip oscillator on, divide-by-4 (f (bclk) = 10 mhz) 125 khz on-chip oscillator stopped 17.0 ma 125 khz on-chip oscillator mode main clock stopped 40 mhz on-chip oscillator stopped 125 khz on-chip oscillator on, no division fmr22 = 1 (slow read mode) 450.0 a low-power mode f (bclk) = 32 mhz in low-power mode fmr 22 = fmr23 = 1 on flash memory (1) 160.0 a f (bclk) = 32 mhz in low-power mode on ram (1) 40.0 a wait mode main clock stopped 40 mhz on-chip oscillator stopped 125 khz on-chip oscillator on peripheral clock operating t opr = 25 c 20.0 a f (bclk) = 32 mhz (oscillation capacity high) 40 mhz on-chip oscillator stopped 125 khz on-chip oscillator stopped peripheral clock operating t opr = 25 c 8.0 a f (bclk) = 32 khz (oscillation capacity low) 40 mhz on-chip oscillator stopped 125 khz on-chip oscillator stopped peripheral clock operating t opr = 25 c 4.0 a stop mode main clock stopped 40 mhz on-chip oscillator stopped 125 khz on-chip oscillator stopped peripheral clock stopped t opr = 25 c 1.6 a during flash memory program f (bclk) = 10 mhz, pm17 = 1 (one wait) v cc1 = 3.0 v 20.0 ma during flash memory erase f (bclk) = 10 mhz, pm17 = 1 (one wait) v cc1 = 3.0 v 30.0 ma
r01ds0031ej0210 rev.2.10 page 89 of 111 jul 31, 2012 m16c/65 group 5. electrical characteristics v cc1 = v cc2 = 3 v note: 1. this indicates the memory in which the program to be executed exists. table 5.45 electrical characteristics (3) r5f3651enfc, r5f3651edfc, r5f3651knfc, r5f3650knfa, r5f3650knfb, r5f3651kdfc, r5f3650kdfa, r5f3650kdfb, r5f3651mnfc, r5f3650mnfa, r5 f3650mnfb, r5f3651mdfc, r5f3650mdfa, r5f3650mdfb, r5f3651nnfc, r5f3650nnfa, r5f3650nnfb, r5f3651ndfc, r5f3650ndfa, r5f3650ndfb v cc1 = v cc2 = 2.7 to 3.3 v, v ss = 0 v at t opr = ? 20 c to 85 c/ ? 40 c to 85 c, f (bclk) = 32 mhz unless otherwise specified. symbol parameter measuring condition standard unit min. typ. max. r fxcin feedback resistance xcin 16 m i cc power supply current in single-chip, mode, the output pin are open and other pins are v ss high-speed mode f (bclk) = 32 mhz xin = 4 mhz (square wave), pll multiplied by 8 125 khz on-chip oscillator stopped 26.0 ma f (bclk) = 32 mhz, a/d conversion xin = 4 mhz (square wave), pll multiplied by 8 125 khz on-chip oscillator stopped 27.0 ma f (bclk) = 20 mhz xin = 20 mhz (square wave) 125 khz on-chip oscillator stopped 17.0 ma 40 mhz on-chip oscillator mode main clock stopped 40 mhz on-chip oscillator on, divide-by-4 (f(bclk) = 10 mhz) 125 khz on-chip oscillator stopped 18.0 ma 125 khz on-chip oscillator mode main clock stopped 40 mhz on-chip oscillator stopped 125 khz on-chip oscillator on, no division fmr22 = 1 (slow read mode) 500.0 a low-power mode f (bclk) = 32 mhz in low-power mode, fmr 22 = fmr23 = 1 on flash memory (1) 170.0 a f (bclk) = 32 mhz in low-power mode, on ram (1) 40.0 a wait mode main clock stopped 40 mhz on-chip oscillator stopped 125 khz on-chip oscillator on peripheral clock operating t opr = 25 c 20.0 a f (bclk) = 32 mhz (oscillation capacity high) 40 mhz on-chip oscillator stopped 125 khz on-chip oscillator stopped peripheral clock operating t opr = 25 c 8.0 a f (bclk) = 32 khz (oscillation capacity low) 40 mhz on-chip oscillator stopped 125 khz on-chip oscillator stopped peripheral clock operating t opr = 25 c 4.0 a stop mode main clock stopped 40 mhz on-chip oscillator stopped 125 khz on-chip oscillator stopped peripheral clock stopped t opr = 25 c 1.6 a during flash memory program f (bclk) = 10 mhz, pm17 = 1 (one wait) v cc1 = 3.0 v 20.0 ma during flash memory erase f (bclk) = 10 mhz, pm17 = 1 (one wait) v cc1 = 3.0 v 30.0 ma
r01ds0031ej0210 rev.2.10 page 90 of 111 jul 31, 2012 m16c/65 group 5. electrical characteristics v cc1 = v cc2 = 3 v note: 1. this indicates the memory in which the program to be executed exists. table 5.46 electrical characteristics (4) r5f3651rnfc, r5f3650rnfa, r5f3650rnfb, r5f3651 rdfc, r5f3650rdfa, r5f3650rdfb, r5f3651tnfc, r5f3650tnfa, r5f3650tnfb, r5f3651tdfc, r5f3650tdfa, r5f3650tdfb v cc1 = v cc2 = 2.7 to 3.3 v, v ss = 0 v at t opr = ? 20 c to 85 c/ ? 40 c to 85 c, f (bclk) = 32 mhz unless otherwise specified. symbol parameter measuring condition standard unit min. typ. max. r fxcin feedback resistance xcin 25 m i cc power supply current in single-chip, mode, the output pin are open and other pins are v ss high-speed mode f (bclk) = 32 mhz xin = 4 mhz (square wave), pll multiplied by 8 125 khz on-chip oscillator stopped 32.0 ma f (bclk) = 32 mhz, a/d conversion xin = 4 mhz (square wave), pll multiplied by 8 125 khz on-chip oscillator stopped 32.7 ma f (bclk) = 20 mhz xin = 20 mhz (square wave) 125 khz on-chip oscillator stopped 21.0 ma 40 mhz on-chip oscillator mode main clock stopped 40 mhz on-chip oscillator on, divide-by-4 (f(bclk) = 10 mhz) 125 khz on-chip oscillator stopped 23.0 ma 125 khz on-chip oscillator mode main clock stopped 40 mhz on-chip oscillator stopped 125 khz on-chip oscillator on, no division fmr22 = 1 (slow read mode) 750.0 a low-power mode f (bclk) = 32 mhz in low-power mode, fmr 22 = fmr23 = 1 on flash memory (1) 300.0 a f (bclk) = 32 mhz in low-power mode, on ram (1) 40.0 a wait mode main clock stopped 40 mhz on-chip oscillator stopped 125 khz on-chip oscillator on peripheral clock operating t opr = 25 c 20.0 a f (bclk) = 32 mhz (oscillation capacity high) 40 mhz on-chip oscillator stopped 125 khz on-chip oscillator stopped peripheral clock operating t opr = 25 c 8.0 a f (bclk) = 32 khz (oscillation capacity low) 40 mhz on-chip oscillator stopped 125 khz on-chip oscillator stopped peripheral clock operating t opr = 25 c 4.0 a stop mode main clock stopped 40 mhz on-chip oscillator stopped 125 khz on-chip oscillator stopped peripheral clock stopped t opr = 25 c 1.6 a during flash memory program f (bclk) = 10 mhz, pm17 = 1 (one wait) v cc1 = 3.0 v 20.0 ma during flash memory erase f (bclk) = 10 mhz, pm17 = 1 (one wait) v cc1 = 3.0 v 30.0 ma
r01ds0031ej0210 rev.2.10 page 91 of 111 jul 31, 2012 m16c/65 group 5. electrical characteristics v cc1 = v cc2 = 3 v 5.3.2 timing requirements (per ipheral functions and others) (v cc1 = v cc2 = 3 v, v ss = 0 v, at t opr = -20 c to 85 c/-40 c to 85 c unless otherwise specified) 5.3.2.1 reset input ( reset input) figure 5.20 reset input ( reset input) 5.3.2.2 external clock input note: 1. the condition is v cc1 = v cc2 = 2.7 to 3.0 v. figure 5.21 external clock input (xin input) table 5.47 reset input ( reset input) symbol parameter standard unit min. max. t w(rstl) reset input low pulse width 10 s table 5.48 external clock input (xin input) (1) symbol parameter standard unit min. max. t c external clock input cycle time 50 ns t w(h) external clock inpu t high pulse width 20 ns t w(l) external clock input low pulse width 20 ns t r external clock rise time 9n s t f external clock fall time 9n s reset input t w(rtsl) xin input t w(h) t r t f t w(l) t c
r01ds0031ej0210 rev.2.10 page 92 of 111 jul 31, 2012 m16c/65 group 5. electrical characteristics v cc1 = v cc2 = 3 v timing requirements (v cc1 = v cc2 = 3 v, v ss = 0 v, at t opr = -20 c to 85 c/-40 c to 85 c unless otherwise specified) 5.3.2.3 timer a input figure 5.22 timer a input table 5.49 timer a input (counter input in event counter mode) symbol parameter standard unit min. max. t c(ta) taiin input cycle time 150 ns t w(tah) taiin input high pulse width 60 ns t w(tal) taiin input low pulse width 60 ns table 5.50 timer a input (gating input in timer mode) symbol parameter standard unit min. max. t c(ta) taiin input cycle time 600 ns t w(tah) taiin input high pulse width 300 ns t w(tal) taiin input low pulse width 300 ns table 5.51 timer a input (external trigger input in one-shot timer mode) symbol parameter standard unit min. max. t c(ta) taiin input cycle time 300 ns t w(tah) taiin input high pulse width 150 ns t w(tal) taiin input low pulse width 150 ns table 5.52 timer a input (external trigger input in pulse width modulation mode and programmable output mode) symbol parameter standard unit min. max. t w(tah) taiin input high pulse width 150 ns t w(tal) taiin input low pulse width 150 ns taiin input taiout input t w(tah) t c(ta) t w(tal) t c(up) t w(uph) t w(upl)
r01ds0031ej0210 rev.2.10 page 93 of 111 jul 31, 2012 m16c/65 group 5. electrical characteristics v cc1 = v cc2 = 3 v timing requirements (v cc1 = v cc2 = 3 v, v ss = 0 v, at t opr = -20 c to 85 c/-40 c to 85 c unless otherwise specified) figure 5.23 timer a input (two-phase pulse input in event counter mode) table 5.53 timer a input (two-phase pulse input in event counter mode) symbol parameter standard unit min. max. t c(ta) taiin input cycle time 2 s t su(tain-taout) taiout input setup time 500 ns t su(taout-tain) taiin input setup time 500 ns taiin input two-phase pulse input in event counter mode taiout input t c(ta) t su(tain-taout) t su(tain-taout) t su(taout-tain) t su(taout-tain)
r01ds0031ej0210 rev.2.10 page 94 of 111 jul 31, 2012 m16c/65 group 5. electrical characteristics v cc1 = v cc2 = 3 v timing requirements (v cc1 = v cc2 = 3 v, v ss = 0 v, at t opr = -20 c to 85 c/-40 c to 85 c unless otherwise specified) 5.3.2.4 timer b input figure 5.24 timer b input table 5.54 timer b input (counter input in event counter mode) symbol parameter standard unit min. max. t c(tb) tbiin input cycle time (counted on one edge) 150 ns t w(tbh) tbiin input high pulse width (counted on one edge) 60 ns t w(tbl) tbiin input low pulse width (counted on one edge) 60 ns t c(tb) tbiin input cycle time (counted on both edges) 300 ns t w(tbh) tbiin input high pulse width (counted on both edges) 120 ns t w(tbl) tbiin input low pulse width (counted on both edges) 120 ns table 5.55 timer b input (pul se period measurement mode) symbol parameter standard unit min. max. t c(tb) tbiin input cycle time 600 ns t w(tbh) tbiin input high pulse width 300 ns t w(tbl) tbiin input low pulse width 300 ns table 5.56 timer b input (pulse width measurement mode) symbol parameter standard unit min. max. t c(tb) tbiin input cycle time 600 ns t w(tbh) tbiin input high pulse width 300 ns t w(tbl) tbiin input low pulse width 300 ns tbiin input t c(tb) t w(tbh) t w(tbl)
r01ds0031ej0210 rev.2.10 page 95 of 111 jul 31, 2012 m16c/65 group 5. electrical characteristics v cc1 = v cc2 = 3 v timing requirements (v cc1 = v cc2 = 3 v, v ss = 0 v, at t opr = -20 c to 85 c/-40 c to 85 c unless otherwise specified) 5.3.2.5 serial interface figure 5.25 serial interface 5.3.2.6 external interrupt inti input figure 5.26 external interrupt inti input table 5.57 serial interface symbol parameter standard unit min. max. t c(ck) clki input cycle time 300 ns t w(ckh) clki input high pulse width 150 ns t w(ckl) clki input low pulse width 150 ns t d(c-q) txdi output delay time 160 ns t h(c-q) txdi hold time 0n s t su(d-c) rxdi input setup time 100 ns t h(c-d) rxdi input hold time 90 ns table 5.58 external interrupt inti input symbol parameter standard unit min. max. t w(inh) inti input high pulse width 380 ns t w(inl) inti input low pulse width 380 ns clki txdi rxdi t c(ck) t w(ckh) t w(ckl) t h(c-q) t d(c-q) t su(d-c) t h(c-d) inti input t w(inl) t w(inh)
r01ds0031ej0210 rev.2.10 page 96 of 111 jul 31, 2012 m16c/65 group 5. electrical characteristics v cc1 = v cc2 = 3 v timing requirements (v cc1 = v cc2 = 3 v, v ss = 0 v, at t opr = -20 c to 85 c/-40 c to 85 c unless otherwise specified) 5.3.2.7 multi-master i 2 c-bus figure 5.27 multi-master i 2 c-bus table 5.59 multi-master i 2 c-bus symbol parameter standard clock mode fast-mode unit min. max. min. max. t buf bus free time 4.7 1.3 s t hd;sta hold time in start condition 4.0 0.6 s t low hold time in scl clock 0 status 4.7 1.3 s t r scl, sda signals? rising time 1000 20 + 0.1 cb 300 ns t hd;dat data hold time 000.9 s t high hold time in scl clock 1 status 4.0 0.6 s f f scl, sda signals? falling time 300 20 + 0.1 cb 300 ns t su;dat data setup time 250 100 ns t su;sta setup time in restart condition 4.7 0.6 s t su;sto stop condition setup time 4.0 0.6 s sda scl p ps sr t low t hd;sta t hd;dat t high t su;dat t su;sta t r t f t hd;sta t su;sto t buf
r01ds0031ej0210 rev.2.10 page 97 of 111 jul 31, 2012 m16c/65 group 5. electrical characteristics v cc1 = v cc2 = 3 v timing requirements (v cc1 = v cc2 = 3 v, v ss = 0 v, at t opr = -20 c to 85 c/-40 c to 85 c unless otherwise specified) 5.3.3 timing requirements (memory expansion mode and microprocessor mode) notes: 1. calculated according to the bclk frequency as follows: 2. calculated according to the bclk frequency as follows: n is 1 for 1 wait setting, 2 for 2 waits setting and 3 for 3 waits setting. 3. calculated according to the bclk frequency as follows: n is 2 for 2 waits setting, 3 for 3 waits setting. 4. calculated according to the bclk frequency as follows: n is 3 for 2 + 3 , 4 for 2 + 4 , 4 for 3 + 4 , 5 for 4 + 5 ,. table 5.60 memory expansion mode and microprocessor mode symbol parameter standard unit min. max. t ac1(rd-db) data input access time (for setting with no wait) (note 1) ns t ac2(rd-db) data input access time (for setting with wait) (note 2) ns t ac3(rd-db) data input access time (when accessing multiplex bus area) (note 3) ns t ac4(rd-db) data input access time (for setting with 2 + 3 or more) (note 4) ns t su(db-rd) data input setup time 50 ns t su(rdy-bclk) rdy input setup time 85 ns t h(rd-db) data input hold time 0ns t h(bclk-rdy) rdy input hold time 0ns 0.5 10 9 f bclk () ns [] n 0.5 + () f bclk () ns [] n 0.5 ? () f bclk () ns [] n 10 9 f bclk () ns []
r01ds0031ej0210 rev.2.10 page 98 of 111 jul 31, 2012 m16c/65 group 5. electrical characteristics figure 5.28 timing diagram memory expansion mode and microprocessor mode ( effective in wait state setting ) rdy input rd bclk (separate bus) (multiplexed bus) rd (separate bus) (multiplexed bus) t su(rdy-bclk) t h(bclk-rdy) measuring conditions y v = v = 3 v cc1 cc2 y input timing voltage: v = 0.6 v, v = 2.4 v il ih y output timing voltage: v = 1.5 v, v = 1.5 v ol oh v = v = 3 v cc1 cc2 wr , wrl , wrh wr , wrl , wrh
r01ds0031ej0210 rev.2.10 page 99 of 111 jul 31, 2012 m16c/65 group 5. electrical characteristics v cc1 = v cc2 = 3 v 5.3.4 switching characteris tics (memory expansion mode and microprocessor mode) (v cc1 = v cc2 = 3 v, v ss = 0 v, at t opr = -20 c to 85 c/-40 c to 85 c unless otherwise specified) 5.3.4.1 in no wait state setting notes: 1. calculated according to the bclk frequency as follows: f (bclk) is 12.5 mhz or less. 2. calculated according to the bclk frequency as follows: 3. this standard value shows the timing when the output is off, and does not show hold time of data bus. hold time of data bus varies wi th capacitor volu me and pull-up (pull-down) resistance value. hold time of data bus is expressed in t = ? cr ln(1 ? v ol /v cc2 ) by a circuit of the right figure. for example, when v ol = 0.2v cc2 , c = 30 pf, r = 1 k , hold time of output low level is t = ? 30 pf 1 k in(1 ? 0.2v cc2 /v cc2 ) = 6.7 ns. table 5.61 memory expansion and microprocessor modes (in no wait state setting) symbol parameter measuring condition standard unit min. max. t d(bclk-ad) address output delay time see figure 5.29 30 ns t h(bclk-ad) address output hold time (in relation to bclk) 0n s t h(rd-ad) address output hold time (in relation to rd) 0n s t h(wr-ad) address output hold time (in relation to wr) (note 2) ns t d(bclk-cs) chip select output delay time 30 ns t h(bclk-cs) chip select output hold time (in relation to bclk) 0n s t d(bclk-ale) ale signal output delay time 25 ns t h(bclk-ale) ale signal output hold time ? 4n s t d(bclk-rd) rd signal output delay time 30 ns t h(bclk-rd) rd signal output hold time 0n s t d(bclk-wr) wr signal output delay time 30 ns t h(bclk-wr) wr signal output hold time 0n s t d(bclk-db) data output delay time (in relation to bclk) 40 ns t h(bclk-db) data output hold time (in relation to bclk) (3) 0n s t d(db-wr) data output delay time (in relation to wr) (note 1) ns t h(wr-db) data output hold time (in relation to wr) (3) (note 2) ns 0.5 10 9 () --------------------- -40 ns [] ? 0.5 10 9 () --------------------- -10 ns [] ? dbi r c
r01ds0031ej0210 rev.2.10 page 100 of 111 jul 31, 2012 m16c/65 group 5. electrical characteristics figure 5.29 ports p0 to p14 measurement circuit p6 p7 p8 p10 p9 p0 p1 p2 p3 p4 p5 30 pf p11 p12 p13 p14
r01ds0031ej0210 rev.2.10 page 101 of 111 jul 31, 2012 m16c/65 group 5. electrical characteristics figure 5.30 timing diagram bclk csi adi ale rd 30ns(max.) 0ns(min.) hi-z dbi 0ns(min.) bhe read timing memory expansion mode and microprocessor mode (in no wait state setting) 30ns(max.) 0ns(min.) bclk csi adi ale bhe 0ns(min.) dbi write timing hi-z 1 f (bclk) v = v = 3v cc1 cc2 25ns(max.) t h(bclk-cs) t cyc t h(bclk-ad) 0ns(min.) t d(bclk-ad) t d(bclk-ale) -4ns(min.) t h(rd-ad) 0ns(min.) t d(bclk-rd) t h(bclk-rd) 0ns(min.) t ac1(rd-db) (0.5 t -60)ns(max.) cyc t su(db-rd) t h(rd-db) t h(bclk-ale) 30ns(max.) t d(bclk-cs) 30ns(max.) t d(bclk-cs) 30ns(max.) 0ns(min.) t h(bclk-cs) t cyc 30ns(max.) 0ns(min.) 25ns(max.) t d(bclk-ale) -4ns(min.) t h(bclk-ale) t d(bclk-ad) t h(bclk-ad) t h(wr-ad) (0.5 t -10)ns(min.) cyc t d(bclk-wr) t h(bclk-wr) t d(bclk-db) t h(bclk-db) t d(db-wr) (0.5 t -40)ns(min.) cyc t h(wr-db) (0.5 t -10)ns(min.) cyc t = cyc 40ns(max.) measuring conditions y v = v = 3v cc1 cc2 y input timing voltage: v = 0.6 v, v = 2.4 v il ih y output timing voltage: v = 1.5 v, v = 1.5 v ol oh 50ns(min.) wr , wrl , wrh
r01ds0031ej0210 rev.2.10 page 102 of 111 jul 31, 2012 m16c/65 group 5. electrical characteristics v cc1 = v cc2 = 3 v switching characteristics (v cc1 = v cc2 = 3 v, v ss = 0 v, at t opr = -20 c to 85 c/-40 c to 85 c unless otherwise specified) 5.3.4.2 in 1 to 3 waits setting and when accessing external area notes: 1. calculated according to the bclk frequency as follows: 2. calculated according to the bclk frequency as follows: 3. this standard value shows the timing when the output is off, and does not show hold time of data bus. hold time of data bus varies with capacitor volume and pull-up (pull-down) resistance value. hold time of data bus is expressed in t = ? cr ln(1 ? v ol /v cc2 ) by a circuit of the right figure. for example, when v ol = 0.2v cc2 , c = 30 pf, r = 1 k , hold time of output low level is t = ? 30 pf 1 k in(1 ? 0.2v cc2 /v cc2 ) = 6.7 ns. table 5.62 memory expansion mode and microprocessor mode (in 1 to 3 waits setting and when accessing external area) symbol parameter measuring condition standard unit min. max. t d(bclk-ad) address output delay time see figure 5.29 30 ns t h(bclk-ad) address output hold time (in relation to bclk) 0n s t h(rd-ad) address output hold time (in relation to rd) 0n s t h(wr-ad) address output hold time (in relation to wr) (note 2) ns t d(bclk-cs) chip select output delay time 30 ns t h(bclk-cs) chip select output hold time (in relation to bclk) 0n s t d(bclk-ale) ale signal output delay time 25 ns t h(bclk-ale) ale signal output hold time -4 ns t d(bclk-rd) rd signal output delay time 30 ns t h(bclk-rd) rd signal output hold time 0n s t d(bclk-wr) wr signal output delay time 30 ns t h(bclk-wr) wr signal output hold time 0n s t d(bclk-db) data output delay time (in relation to bclk) 40 ns t h(bclk-db) data output hold time (in relation to bclk) (3) 0n s t d(db-wr) data output delay time (in relation to wr) (note 1) ns t h(wr-db) data output hold time (in relation to wr) (3) (note 2) ns n is 1 for 1 wait setting, 2 for 2 waits setting and 3 for 3 waits setting. when n = 1, f (bclk) is 12.5 mhz or less. n 0.5 ? () f bclk () ns [] f bclk () ns [] dbi r c
r01ds0031ej0210 rev.2.10 page 103 of 111 jul 31, 2012 m16c/65 group 5. electrical characteristics figure 5.31 timing diagram bclk csi adi ale rd hi-z dbi bhe read timing bclk csi adi ale bhe dbi write timing hi-z memory expansion mode and microprocessor mode (in 1 to 3 waits setting and when accessing external area) 1 v = v = 3v cc1 cc2 t d(bclk-cs) 30ns(max.) 0ns(min.) t cyc t h(bclk-ad) t d(bclk-ad) 30ns(max.) t d(bclk-ale) 25ns(max.) 0ns(min.) t h(bclk-cs) -4ns(min.) t h(bclk-ale) 0ns(min.) t h(rd-ad) t d(bclk-rd) 30ns(max.) 0ns(min.) t h(bclk-rd) t su(db-rd) 0ns(min.) t h(rd-db) t d(bclk-cs) 30ns(max.) 0ns(min.) t h(bclk-cs) t cyc t d(bclk-ad) 30ns(max.) 0ns(min.) t h(bclk-ad) t d(bclk-ale) 25ns(max.) -4ns(min.) t h(bclk-ale) (0.5 t -10)ns(min.) cyc t h(wr-ad) t d(bclk-wr) 30ns(max.) 0ns(min.) t h(bclk-wr) t d(bclk-db) 40ns(max.) 0ns(min.) t h(wr-db) t d(db-wr) {(n-0.5) t -40}ns(min.) cyc (0.5 t -10)ns(min.) cyc t = cyc t h(bclk-db) n: 1 (when 1 wait) 2 (when 2 waits) 3 (when 3 waits) measuring conditions y v = v = 3v cc1 cc2 y input timing voltage: v = 0.6 v, v = 2.4 v il ih y output timing voltage: v = 1.5 v, v = 1.5 v ol oh f (bclk) {(n+0.5) t -60}ns(max.) cyc t ac2(rd-db) 50ns(min.) wr , wrl , wrh
r01ds0031ej0210 rev.2.10 page 104 of 111 jul 31, 2012 m16c/65 group 5. electrical characteristics v cc1 = v cc2 = 3 v switching characteristics (v cc1 = v cc2 = 3 v, v ss = 0 v, at t opr = -20 c to 85 c/-40 c to 85 c unless otherwise specified) 5.3.4.3 in 2 or 3 waits setting, and when accessing external area and using multiplexed bus notes: 1. calculated according to the bclk frequency as follows: 2. calculated according to the bclk frequency as follows: n is 2 for 2 waits setting, 3 for 3 waits setting. 3. calculated according to the bclk frequency as follows: 4. calculated according to the bclk frequency as follows: 5. when using multiplexed bus, set f (bclk) 12.5 mhz or less. table 5.63 memory expansion mode and microprocess or mode (in 2 or 3 waits setting, and when accessing external area and using multiplexed bus) (5) symbol parameter measuring condition standard unit min. max. t d(bclk-ad) address output delay time see figure 5.29 50 ns t h(bclk-ad) address output hold time (in relation to bclk) 0n s t h(rd-ad) address output hold time (in relation to rd) (note 1) ns t h(wr-ad) address output hold time (in relation to wr) (note 1) ns t d(bclk-cs) chip select output delay time 50 ns t h(bclk-cs) chip select output hold time (in relation to bclk) 0n s t h(rd-cs) chip select output hold time (in relation to rd) (note 1) ns t h(wr-cs) chip select output hold time (in relation to wr) (note 1) ns t d(bclk-rd) rd signal output delay time 40 ns t h(bclk-rd) rd signal output hold time 0n s t d(bclk-wr) wr signal output delay time 40 ns t h(bclk-wr) wr signal output hold time 0n s t d(bclk-db) data output delay time (in relation to bclk) 50 ns t h(bclk-db) data output hold time (in relation to bclk) 0n s t d(db-wr) data output delay time (in relation to wr) (note 2) ns t h(wr-db) data output hold time (in relation to wr) (note 1) ns t d(bclk-ale) ale signal output delay time (in relation to bclk) 25 ns t h(bclk-ale) ale signal output hold time (in relation to bclk) ? 4n s t d(ad-ale) ale signal output delay time (in relation to address) (note 3) ns t h(ad-ale) ale signal output hold time (in relation to address) (note 4) ns t d(ad-rd) rd signal output delay from the end of address 0n s t d(ad-wr) wr signal output delay from the end of address 0n s t dz(rd-ad) address output floating start time 8ns 0.5 10 9 () --------------------- -10 ns [] ? n 0.5 ? () 10 9 () ----------------------------------- -50 ns [] ? 0.5 10 9 () --------------------- -40 ns [] ? 0.5 10 9 () --------------------- -15 ns [] ?
r01ds0031ej0210 rev.2.10 page 105 of 111 jul 31, 2012 m16c/65 group 5. electrical characteristics figure 5.32 timing diagram memory expansion mode and microprocessor mode (in 2 or 3 waits setting, and when accessing external area and using multiplexed bus ) bclk csi adi ale rd bhe adi /dbi read timing bclk csi adi ale bhe adi /dbi data output write timing address address data input address address v = v = 3v cc1 cc2 t d(bclk-cs) 50ns(max.) t cyc (0.5 t -10)ns(min.) cyc t h(rd-cs) t h(bclk-cs) 0ns(min.) (0.5 t -40ns(min.) cyc t d(ad-ale) (0.5 t -15ns(min.) cyc t h(ale-ad) t dz(rd-ad) 8ns(max.) {(n-0.5) t -60}ns(max.) cyc t ac3(rd-db) t su(db-rd) t h(rd-db) 0ns(min.) 0ns(min.) t d(ad-rd) t h(bclk-ad) 0ns(min.) 25ns(max.) t d(bclk-ale) t h(bclk-ale) -4ns(min.) t d(bclk-ad) 50ns(max.) t h(rd-ad) (0.5 t -10)ns(min.) cyc 40ns(max.) t d(bclk-rd) 0ns(min.) t h(bclk-rd) t cyc t d(bclk-cs) 50ns(max.) (0.5 t -10)ns(min.) cyc t h(wr-cs) t h(bclk-cs) 0ns(min.) t d(bclk-db) 50ns(max.) t h(bclk-db) 0ns(min.) (0.5 t -40ns(min.) cyc t d(ad-ale) {(n-0.5) t -50}ns(min.) cyc t d(db-wr) (0.5 t -10)ns(min.) cyc t h(wr-db) t d(bclk-ad) 50ns(max.) t h(bclk-ad) 0ns(min.) 25ns(max.) t d(bclk-ale) t h(bclk-ale) -4ns(min.) 0ns(min.) t d(ad-wr) t h(wr-ad) (0.5 t -10)ns(min.) cyc 40ns(max.) t d(bclk-wr) 0ns(min.) t h(bclk-wr) n: 2 (when 2 waits) 3 (when 3 waits) measuring conditions y v = v = 3v cc1 cc2 y input timing voltage: v = 0.6 v, v = 2.4 v il ih y output timing voltage: v = 1.5 v, v = 1.5 v ol oh 1 t = cyc f (bclk) 50ns(min.) wr , wrl , wrh
r01ds0031ej0210 rev.2.10 page 106 of 111 jul 31, 2012 m16c/65 group 5. electrical characteristics v cc1 = v cc2 = 3 v switching characteristics (v cc1 = v cc2 = 3 v, v ss = 0 v, at t opr = -20 c to 85 c/-40 c to 85 c unless otherwise specified) 5.3.4.4 in wait state setting 2 + 3 , 2 + 4 , 3 + 4 , and 4 + 5 , and when accessing external area notes: 1. calculated according to the bclk frequency as follows: 2. calculated according to the bclk frequency as follows: 3. this standard value shows the timing when the output is off, and does not show hold time of data bus. hold time of data bus varies with capacitor volume and pull- up (pull-down) resistance value. hold time of data bus is expressed in t = ? cr ln(1 ? v ol /v cc2 ) by a circuit of the right figure. for example, when v ol = 0.2v cc2 , c = 30 pf, r = 1 k , hold time of output low level is t = ? 30 pf 1 k in(1 ? 0.2v cc2 /v cc2 ) = 6.7 ns. table 5.64 memory expansion and microprocessor modes (in wait state setting 2 + 3 , 2 + 4 , 3 + 4 , and 4 + 5 , and when accessing external area) symbol parameter measuring condition standard unit min. max. t d(bclk-ad) address output delay time see figure 5.29 30 ns t h(bclk-ad ) address output hold time (in relation to bclk) 0n s t h(rd-ad ) address output hold time (in relation to rd) 0n s t h(wr-ad) address output hold time (in relation to wr) (note 2) ns t d(bclk-cs) chip select output delay time 30 ns t h(bclk-cs) chip select output hold time (in relation to bclk) 0n s t d(bclk-ale) ale signal output delay time 25 ns t h(bclk-ale ) ale signal output hold time -4 ns t d(bclk-rd) rd signal output delay time 30 ns t h(bclk-rd) rd signal output hold time 0n s t d(bclk-wr) wr signal output delay time 30 ns t h(bclk-wr) wr signal output hold time 0n s t d(bclk-db) data output delay time (in relation to bclk) 40 ns t h(bclk-db) data output hold time (in relation to bclk) (3) 0n s t d(db-wr) data output delay time (in relation to wr) (note 1) ns t h(wr-db) data output hold time (in relation to wr) (3) (note 2) ns n 0.5 ? () f bclk () ns [] n is 3 for 2 + 3 , 4 for 2 + 4 , 4 for 3 + 4 , and 5 for 4 + 5 . 0.5 10 9 f bclk () ns [] dbi r c
r01ds0031ej0210 rev.2.10 page 107 of 111 jul 31, 2012 m16c/65 group 5. electrical characteristics figure 5.33 timing diagram read timing write timing bclk csi ale dbi adi bhe wr, wrl wrh bclk csi ale dbi adi bhe rd t cyc t d(bclk-cs) 30ns(max.) t d(bclk-ad) 30ns(max.) t d(bclk-ale) 25ns(max.) t h(bclk-ale) -4ns(min.) t d(bclk-rd) 30ns(max.) hi-z t su(db-rd) hi-z t d(bclk-cs) 30ns(max.) t d(bclk-ad) 30ns(max.) t d(bclk-ale) 25ns(max.) t d(bclk-wr) 30ns(max.) (0.5 t -10)ns(min.) cyc t ac4(rd-db) (n t -60)ns(max.) cyc v = v = 3v cc1 cc2 memory expansion mode, microprocessor mode (in wait state setting 2 + 3 , 2 + 4 , 3 + 4 , and 4 + 5 , and when accessing external area) n: 3 (when 2 + 3 ) 4 (when 2 + 4 or 3 + 4 ) 5 (when 4 + 5 ) t h(bclk-ad) 0ns(min.) t h(bclk-cs) 0ns(min.) t h(rd-ad) 0ns(min.) t h(bclk-rd) 0ns(min.) t h(rd-db) 0ns(min.) t h(bclk-cs) 0ns(min.) t h(bclk-ad) 0ns(min.) t h(bclk-ale) -4ns(min.) t h(wr-ad) t h(bclk-wr) 0ns(min.) t d(db-wr) t h(bclk-db) 0ns(min.) {(n-0.5) t -40}ns(min.) cyc t h(wr-db) (0.5 t -10)ns(min.) cyc measuring conditions y v = v = 3v cc1 cc2 y input timing voltage: v = 0.6 v, v = 2.4 v il ih y output timing voltage: v = 1.5 v, v = 1.5 v ol oh t cyc = 1 f(bclk) t cyc t d(bclk-db) 40ns(max.) 50ns(min.)
r01ds0031ej0210 rev.2.10 page 108 of 111 jul 31, 2012 m16c/65 group 5. electrical characteristics v cc1 = v cc2 = 3 v switching characteristics (v cc1 = v cc2 = 3 v, v ss = 0 v, at t opr = -20 c to 85 c/-40 c to 85 c unless otherwise specified) 5.3.4.5 in wait state setting 2 + 3 , 2 + 4 , 3 + 4 , and 4 + 5 , and inserting 1 to 3 recovery cycles and accessing external area notes: 1. calculated according to the bclk frequency as follows: 2. calculated according to the bclk frequency as follows: 3. this standard value shows the timing when the output is off, and does not show hold time of data bus. hold time of data bus varies with capacitor volume and pull-up (pull-down) resistance value. hold time of data bus is expressed in t = ? cr ln(1 ? v ol /v cc2 ) by a circuit of the right figure. for example, when v ol = 0.2v cc2 , c = 30 pf, r = 1 k , hold time of output low level is t = ? 30 pf 1 k in(1 ? 0.2v cc2 /v cc2 ) = 6.7 ns. 4. calculated according to the bclk frequency as follows: table 5.65 memory expansion mode and microprocessor mode (in wait state setting 2 + 3 , 2 + 4 , 3 + 4 , and 4 + 5 , and inserting 1 to 3 recovery cycles and accessing external area) symbol parameter measuring condition standard unit min. max. t d(bclk-ad) address output delay time see figure 5.29 30 ns t h(bclk-ad ) address output hold time (in relation to bclk) 0ns t h(rd-ad ) address output hold time (in relation to rd) (note 4) ns t h(wr-ad) address output hold time (in relation to wr) (note 2) ns t d(bclk-cs) chip select output delay time 30 ns t h(bclk-cs) chip select output hold time (in relation to bclk) 0n s t d(bclk-ale) ale signal output delay time 25 ns t h(bclk-ale ) ale signal output hold time -4 ns t d(bclk-rd) rd signal output delay time 30 ns t h(bclk-rd) rd signal output hold time 0n s t d(bclk-wr) wr signal output delay time 30 ns t h(bclk-wr) wr signal output hold time 0n s t d(bclk-db) data output delay time (in relation to bclk) 40 ns t h(bclk-db) data output hold time (in relation to bclk) (3) 0n s t d(db-wr) data output delay time (in relation to wr) (note 1) ns t h(wr-db) data output hold time (in relation to wr) (3) (note 2) ns n 10 9 f bclk () ns [] n is 3 for 2 + 3 , 4 for 2 + 4 , 4 for 3 + 4 , and 5 for 4 + 5 . m 10 9 f bclk () ns [] m is 1 when 1 recovery cycle is inserted, 2 when 2 recovery cycles are inserted, and 3 when 3 recovery cycles are inserted. dbi r c m 10 9 f bclk () ns [] m is 1 when 1 recovery cycle is inserted, 2 when 2 recovery cycles are inserted, and 3 when 3 recovery cycles are inserted.
r01ds0031ej0210 rev.2.10 page 109 of 111 jul 31, 2012 m16c/65 group 5. electrical characteristics figure 5.34 timing diagram read timing write timing bclk csi ale dbi adi bhe wr, wrl wrh bclk csi ale dbi adi bhe rd t cyc t d(bclk-cs) 30ns(max.) hi-z t su(db-rd) hi-z v = v = 3v cc1 cc2 memory expansion mode and microprocessor mode (in wait state setting 2 + 3 , 2 + 4 , 3 + 4 , and 4 + 5 , and when inserting 1 to 3 recovery cycles inserted and accessing external area) n: 3 (when 2 + 3 ) 4 (when 2 + 4 or 3 + 4 ) 5 (when 4 + 5 ) t h(bclk-cs) 0ns(min.) t d(bclk-ad) 30ns(max.) t h(bclk-ad) 0ns(min.) t d(bclk-ale) 25ns(max.) t h(bclk-ale) -4ns(min.) t d(bclk-rd) 30ns(max.) t h(bclk-rd) 0ns(min.) t h(rd-db) 0ns(min.) t cyc t d(bclk-cs) 30ns(max.) t d(bclk-ad) 30ns(max.) t h(bclk-ale) -4ns(min.) t d(bclk-ale) 25ns(max.) t d(bclk-wr) 30ns(max.) t d(bclk-db) 40ns(max.) t h(bclk-cs) 0ns(min.) t h(bclk-ad) 0ns(min.) t h(wr-ad) (m t -10)ns(min.) cyc t h(bclk-wr) 0ns(min.) t h(bclk-db) 0ns(min.) t h(wr-db) (m t -10)ns(min.) cyc (n t -60)ns(max.) cyc t ac4(rd-db) (n t -40)ns(min.) cyc t d(db-wr) t cyc = 1 f(bclk) m: 1 (when 1 recovery cycle inserted ) 2 (when 2 recovery cycles inserted) 3 (when 3 recovery cycles inserted) measuring conditions y v = v = 3v cc1 cc2 y input timing voltage: v = 0.6 v, v = 2.4 v il ih y output timing voltage: v = 1.5 v, v = 1.5 v ol oh t h(rd-ad) (m t +0)ns(min.) cyc 50ns(min.)
r01ds0031ej0210 rev.2.10 page 110 of 111 jul 31, 2012 m16c/65 group appendix 1. package dimensions appendix 1. package dimensions the information on the latest package dimensions or packaging may be obtained from ?packages? on the renesas electronics website. 2. 1. dimensions " *1" and " *2" do not include mold flash. note) dimension " *3" does not include trim offset. detailf l 1 c a a 1 a 2 l index mark y x f 1 38 39 64 65 102 103 128 *1 *3 *2 z e z d d h d e h e b p l 1 z e z d c 1 b 1 b p a 1 h e h d y 0.10 e 0.5 c 0 8 x l 0.35 0.5 0.65 0.05 0.125 0.2 a 1.7 15.8 16.0 16.2 21.8 22.0 22.2 a 2 1.4 e 13.9 14.0 14.1 d 19.9 20.0 20.1 reference symbol dimension in millimeters min nom max 0.17 0.22 0.27 0.09 0.145 0.20 0.10 0.75 0.75 0.20 0.125 1.0 p-lqfp128-14x20-0.50 0.9g mass[typ.] 128p6q-a plqp0128kb-a renesas code jeita package code previous code terminal cross section c bp c 1 b 1 e p-qfp100-14x20-0.65 1.8g mass[typ.] 100p6f-a prqp0100jd-b renesas code jeita package code previous code 0.2 0.150.13 0.40.3 0.25 maxnommin dimension in millimeters symbol reference 20.220.019.8 d 14.214.013.8 e 2.8 a 2 23.122.822.5 17.116.816.5 3.05 a 0.20.1 0 0.80.60.4 l 10 0 c 0.65 e 0.10 y h d h e a 1 b p z d z e 0.575 0.825 x 0.13 2. 1. dimensions " *1" and "*2" do not include mold flash. note) dimension "*3" does not include trim offset. detail f l a 2 a 1 *3 *1 *2 f 1 30 31 50 51 80 81 100 index mark y x c h e e d h d a b p z d z e e
r01ds0031ej0210 rev.2.10 page 111 of 111 jul 31, 2012 m16c/65 group appendix 1. package dimensions terminal cross section b 1 c 1 b p c 2. 1. dimensions " *1" and "*2" do not include mold flash. note) dimension "*3" does not include trim offset. y index mark x 12 5 26 50 51 75 76 100 f *1 *3 *2 z e z d e d h d h e b p detail f l 1 a 2 a 1 l a c l 1 z e z d c 1 b 1 b p a 1 h e h d y 0.08 e 0.5 c 0 8 x l 0.35 0.5 0.65 0.05 0.1 0.15 a 1.7 15.8 16.0 16.2 15.8 16.0 16.2 a 2 1.4 e 13.9 14.0 14.1 d 13.9 14.0 14.1 reference symbol dimension in millimeters min nom max 0.15 0.20 0.25 0.09 0.145 0.20 0.08 1.0 1.0 0.18 0.125 1.0 previous code jeita package code renesas code plqp0100kb-a 100p6q-a / fp-100u / fp-100uv mass[typ.] 0.6g p-lqfp100-14x14-0.50 e
a - 1 revision history m16c/65 group datasheet rev. date description page summary 1.00 feb 02, 2009 - first edition issued. 1.10 sep 24, 2009 3 table 1.2 specifications fo r the 128-pin package (2/2) partially modified 5 table 1.4 specifications for the 100-pin package (2/2) partially modified 6 table 1.5 product list (1/2) partially modified 7 table 1.6 product list (2/2) partially modified 8 figure 1.2 marking diagram (top view) partially modified 29 figure 3.2 memory map 13800h 13000h 32 table 4.2 ?sfr information (2/16)?notes partially modified 48 table 5.1 absolute maximum ratings partially modified 49 table 5.2 recommended operating conditions (1/3) partially modified 50 table 5.3 recommended operating conditions (2/3) partially modified 51 table 5.4 recommended operating conditions (3/3) added 51 figure 5.1 ripple waveform added 52 table 5.5 a/d conversion charac teristics (1/2) partially modified 52 figure 5.2 a/d accuracy measure circuit added 53 table 5.6 a/d conversion charac teristics (2/2) partially modified 55 table 5.8 cpu clock when operating flash memory (f (bclk) ) partially modified 55 table 5.9 flash memory (program rom 1, 2) electrical characteristics partially modified 56 table 5.10 flash memory (data flash) electrical characteristics notes modified 57 table 5.11 voltage detector 0 electr ical characteristics partially modified 57 table 5.12 voltage detector 1 electric al characteristics partially modified 58 table 5.13 voltage detector 2 electric al characteristics partially modified 58 table 5.14 power-on reset circuit partially modified 59 figure 5.3 power-on reset circuit electrical characteristics 0.1 v v por1 61 table 5.16 40 mhz on-chip oscillator circuit elec trical characteristics (1/2) partially modified 61 table 5.17 40 mhz on-chip oscillator circ uit electrical characteristics (2/2) added 61 table 5.18 125 khz on-chip oscillator circui t electrical characteristics partially modified 63 table 5.20 electrical characte ristics (2) partially modified 64 table 5.21 electrical characte ristics (3) partially modified 65 table 5.22 electrical characte ristics (4) partially modified 66 table 5.23 electrical characte ristics (5) partially modified 67 table 5.24 reset input ( reset input) partially modified 85 table 5.42 electrical characte ristics (1) partially modified 87 table 5.44 electrical characte ristics (3) partially modified 88 table 5.45 electrical characte ristics (4) partially modified 89 table 5.46 electrical characte ristics (5) partially modified 90 table 5.47 reset input ( reset input) partially modified 2.00 dec 10, 2010 overall 001ah voltage detector operation enable register: changed reset value from ?000x 0000b?. overall 002ah voltage monitor 0 control regi ster: changed reset value from ?1100 xx10b?. overall 002bh voltage monitor 1 control regi ster: changed reset value from ?1000 1x10b?. overall 0324h increment/decrement flag: changed name from up/down flag. overall 03dch d/a control register: changed reset value from ?xxxx xx00b?. overall d08ah to d08bh pmc0 counter value register: deleted. overall d09eh to d09fh pmc1 counter value register: deleted. overview 3, 5 table 1.2 and table 1.4 specifications for the 128/100-pin package: deleted note 1. 6 table 1.5 product list (1/2): changed the development status. 19, 22 table 1.12 and table 1.15 pin functions: changed the descriptions of the hold pin. address space 29 figure 3.2 memory map: added note 1 and 3 to the reserved areas.
a - 2 2.00 dec 10, 2010 special function registers (sfrs) 31 table 4.1 sfr information (1): ? deleted ?the vcr1 register, the vcr2 register? from note 2. ? deleted notes 5 to 6 and added note 5. 32 table 4.2 sfr information (2): deleted notes 2 to 7 and added note 2. 49 4.2.1 register settings: added the description regarding read-modify-write instructions. 50 table 4.20 read-modify-write instructions: added. electrical characteristics 51 table 5.1 absolute maximum ratings: added a row for the data area value to t opr (flash program erase). 52 table 5.2 recommended operating conditions (1/3): added rows for the cec value to v cc1 , v cc2 , v ih , and v il . 57 table 5.9 flash memory (program rom 1, 2) electrical characteristics: added a condition to the read voltage row. 60 table 5.14 power-on reset circuit: ? added the t w(por) row. ? added the last line in note 1. 60 figure 5.3 power-on reset circuit electr ical characteristics: deleted note 2. 64 table 5.20 electrical char acteristics (2): added ?zp, idu, idv, idw? to the v t+ - v t- row. 65 table 5.21 electrical characteristics (3): moved r5f3651enfc and r5f3651edfc to table 5.22 electrical characteristics (4). 73, 96 5.2.2.7 and 5.3.2.7 multi-master i 2 c-bus: added. 74 to 81, 97 to 104 table 5.37 to table 5.42 and table 5.60 to table 5.65 memory expansion mode and microprocessor mode: deleted the following: ? hold input setup time ? hold input hold time ? hlda output delay time 74 table 5.37 memory expansion mode and microprocessor mode: changed rdy input setup time from 30. 75, 98 figure 5.13 and figure 5.28 timing diagram: deleted lower figure (common to wait state and no wait state settings). 86, 109 figure 5.19 and figure 5.34 timing diagram: changed the width of th(rd-ad). 87 table 5.43 electrical characteristics (1): ? added rows for the cec value to v ol , v t+ -v t- , and leakage current in powered-off state. ? added ?zp, idu, idv, idw? to the v t+ - v t- row. 88 table 5.44 electrical characteristics (2): moved r5f3651enfc and r5f3651edfc to table 5.45 electrical characteristics (3). 88 to 90 table 5.44 to table 5.46 electrical characte ristics (2) to (4): changed ?vcc1 = 5.0 v? to "vcc1 = 3.0 v" in the during flash memory program and during flash memory erase rows. 97 table 5.60 memory expansion mode and microprocessor mode: changed rdy input setup time from 40. 2.10 ju. 31, 2012 electrical characteristics vcc = 5 v 65, 66, 67 table 5.21 electrical characteri stics (3), table 5.22 electrical characteristics (4), and table 5.23 electrical characteristics (5): changed the meas uring condition column of 40 mhz on-chip oscillator for the 40 mhz on-chip oscillator mode in the i cc . vcc = 3 v 88, 89, 90 table 5.44 electrical characteri stics (2), table 5.45 electrical characteristics (3), and table 5.46 electrical characteristics (4): changed the meas uring condition column of 40 mhz on-chip oscillator for the 40 mhz on-chip oscillator mode in the i cc . revision history m16c/65 group datasheet rev. date description page summary all trademarks and registered trademarks are the property of their respective owners. hdmi and high-definition multimedia interface ar e registered trademarks of hdmi licensing, llc.
general precautions in the handling of mpu/mcu products the following usage notes are applicable to all mpu/mcu products from renesas. for detailed usage notes on the products covered by this manual, refer to the rele vant sections of the manu al. if the descriptions under general precautions in the handling of mpu/mcu products and in the body of the manual differ from each other, the description in the bod y of the manual takes precedence. 1. handling of unused pins handle unused pins in accord with the directions given under handling of unused pins in the manual. ? the input pins of cmos products are general ly in the high-impedance state. in operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of lsi, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. unused pins should be handled as described under handling of unused pins in the manual. 2. processing at power-on the state of the product is undefined at the moment when power is supplied. ? the states of internal circuits in the lsi are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. in a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. in a similar way, the states of pins in a pr oduct that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. prohibition of access to reserved addresses access to reserved addresses is prohibited. ? the reserved addresses are provided for the po ssible future expansion of functions. do not access these addresses; the correct operat ion of lsi is not guaranteed if they are accessed. 4. clock signals after applying a reset, only release the reset line after the operating clock signal has become stable. when switching the clock signal during pr ogram execution, wait until the target clock signal has stabilized. ? when the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset li ne is only released after full stabilization of the clock signal. moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. differences between products before changing from one product to another, i.e. to one with a different part number, confirm that the change will not lead to problems. ? the characteristics of mpu/mcu in the same group but having different part numbers may differ because of the differences in internal memory capacity and layout pattern. when changing to products of different part numbe rs, implement a system-evaluation test for each of the products.
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